Design Rule Check (DRC) is the automated verification step that scans every polygon in a chip's layout against the foundry's manufacturing rules — flagging any geometry that would cause a systematic yield failure if sent to fabrication. A DRC deck encodes 3000–5000 rules at a 3 nm node, covering minimum width, spacing, enclosure, area, density, antenna ratio, and multi-patterning color assignment for every layer in the BEOL and FEOL. Zero DRC violations is a hard tape-out gate: foundries will not accept a GDS with known rule violations.

Why DRC exists — the link between design and yield. Every lithographic and etch step has physical limits: optics can't resolve features below a minimum pitch, CMP can't planarize if metal density is too high or too low, and electroplating can't fill a via that's too narrow relative to its depth. DRC rules are the foundry's quantified expression of these limits — derived from process development experiments (split lots, short-loop test structures) and optical simulations. A single rule violation can create a repeating defect across every die on every wafer, making DRC the first and most critical line of defense against systematic yield loss.

Categories of design rules:

DRC vs LVS — the verification pair. DRC checks that every shape is manufacturable; Layout-Versus-Schematic (LVS) checks that the layout implements the correct circuit. Both must pass clean before tape-out:

• DRC: "Is every polygon legal?" — purely geometric, no circuit knowledge.
• LVS: "Does this layout match the schematic netlist?" — extracts devices and connectivity from layout, compares to the intended design.

A layout can pass DRC (all shapes are legal) but fail LVS (a wire is connected to the wrong net). Conversely, it can pass LVS (correct connectivity) but fail DRC (a spacing violation that would short in manufacturing). Both tools run the same extracted layout database but apply fundamentally different checks.

How DRC tools work — the engine. Modern DRC engines (Siemens Calibre, Synopsys ICV, Cadence Pegasus) perform geometric Boolean operations on the full-chip layout:

1. Layer derivation: Combine drawn layers using AND/OR/NOT/SIZE operations to derive process-intent layers (e.g., "active AND poly = gate"). 2. Edge-based and polygon-based checks: For each rule, find all pairs of edges or polygons within interaction distance and test the rule predicate (width, spacing, enclosure, area). 3. Hierarchical processing: Exploit the design's cell hierarchy to avoid checking identical standard cells billions of times — only check unique cell interiors once, then verify cell-to-cell abutment. 4. Error reporting: Output a database of violations with coordinates, rule ID, and violating polygons — designers view these in the layout editor and fix them.

Runtime at 3 nm on a full GPU (~800 mm² equivalent flat): 12–48 hours on a 100+ core server with 500 GB+ RAM, producing millions of initial violations on first pass that are iterated down to zero through ECO fixes.

Multi-patterning DRC — coloring rules. At 7 nm and below, the tightest metal pitches (28–36 nm) are below the resolution of a single lithographic exposure. Self-aligned double/quadruple patterning (SADP/SAQP) or EUV multi-patterning splits one design layer into 2–4 physical masks. The DRC deck must verify:

• Coloring legality: features assigned to the same mask must be spaced ≥ the single-mask resolution limit.
• Tip-to-tip same-color: line ends on the same mask must maintain extra spacing.
• Odd-cycle detection: layouts that create geometric conflicts with no valid coloring assignment (requires a design change, not just re-coloring).

At N3/N2, coloring constraints add 500–1000 rules on top of the baseline geometric DRC.

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  <text x="380" y="28" fill="#c9c3f2" font-size="15" text-anchor="middle" font-weight="600">DRC — design rule categories and verification flow</text>

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  <text x="50" y="55" fill="#8a8a86" font-size="11">Common DRC violations (exaggerated for clarity)</text>

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  <text x="95" y="103" fill="#bf4040" font-size="8">too narrow!</text>
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  <text x="462" y="103" fill="#bf4040" font-size="7">via overhang</text>
  <text x="445" y="130" fill="#8a8a86" font-size="8" text-anchor="middle">Enclosure</text>

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  <text x="605" y="110" fill="#bf4040" font-size="8" text-anchor="middle">density <20%</text>
  <text x="605" y="130" fill="#8a8a86" font-size="8" text-anchor="middle">Density (fill needed)</text>

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  <text x="130" y="233" fill="#bff0bf" font-size="9" text-anchor="middle">GDS layout</text>

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  <text x="267" y="227" fill="#c9c3f2" font-size="9" text-anchor="middle">DRC engine</text>
  <text x="267" y="241" fill="#8a8a86" font-size="7" text-anchor="middle">(Calibre/ICV/Pegasus)</text>

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  <text x="404" y="227" fill="#f0bfbf" font-size="9" text-anchor="middle">Violations DB</text>
  <text x="404" y="241" fill="#8a8a86" font-size="7" text-anchor="middle">(coordinates + rule ID)</text>

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  <text x="531" y="227" fill="#e8d44d" font-size="9" text-anchor="middle">Fix (ECO)</text>
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  <text x="648" y="227" fill="#bff0bf" font-size="9" text-anchor="middle">DRC clean</text>
  <text x="648" y="241" fill="#6fbf6f" font-size="7" text-anchor="middle">→ tape-out</text>

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  <text x="210" y="330" fill="#c9c3f2" font-size="12" text-anchor="middle" font-weight="500">DRC complexity scaling</text>

  <text x="70" y="355" fill="#d4d4d0" font-size="10">130 nm: ~200 rules · minutes to run</text>
  <text x="70" y="375" fill="#d4d4d0" font-size="10">45 nm: ~800 rules · hours</text>
  <text x="70" y="395" fill="#d4d4d0" font-size="10">7 nm: ~2000 rules + MP coloring</text>
  <text x="70" y="415" fill="#e0913a" font-size="10">3 nm: ~4000 rules + SAQP · 12–48 hrs</text>
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  <text x="480" y="365" fill="#e8d44d" font-size="9" text-anchor="middle">DRC: is it printable?</text>
  <text x="480" y="378" fill="#8a8a86" font-size="8" text-anchor="middle">geometric only</text>

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  <text x="560" y="430" fill="#8a8a86" font-size="9" text-anchor="middle">DRC clean ≠ LVS clean (independent checks)</text>

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Waivers and known violations. Not every DRC violation is a true error — some are intentional (analog layout tricks, test structures, or legacy IP blocks that have proven silicon). Designers submit waiver requests with justification; the foundry reviews and grants a limited "DRC waiver" for specific rules at specific coordinates. Waivered violations are tracked but don't block tape-out. At advanced nodes, waiver management is itself a significant engineering effort — a complex SoC may carry 100–500 waivers.

What DRC means for AI accelerator development. A 3 nm GPU tape-out takes 6–12 months of DRC closure iteration. The first full-chip DRC run typically shows millions of violations; the team iterates through macro-level fixes (fill insertion, spacing adjustments, via doubling), standard-cell swaps, and routing ECOs to converge to zero. At 2 nm with BSPDN, designers face additional DRC rules for the backside metal layers and nano-TSVs — rules that have never existed before. DRC closure time is the longest single task in the physical-design schedule, accounting for 20–30% of total design-to-tape-out time.