Physical Verification (DRC/LVS) is a mandatory final-stage design verification ensuring manufactured chip complies with process design rules and schematic matches layout electrical connectivity, preventing yield-killing defects and functional failures.

Design Rule Check (DRC) Overview

• Design Rules: Manufacturing constraints enforced by foundry (TSMC, Samsung, Intel). Rules prevent defects: minimum width (prevents disconnection), minimum spacing (prevents shorts), antenna ratio (ESD damage prevention).
• Layer-Based Rules: Rules apply to individual layers (metal1, via1, poly, diffusion). Example: metal1 minimum width = 32nm (N7 technology).
• Cross-Layer Rules: Rules between layers. Example: minimum metal-to-via overlap = 10nm (ensures via resistance consistency).
• DRC Violations: Red markers indicate rule violations. Typical violations: shorts (spacing too small), opens (width too small), antenna, via density mismatches.

Layout vs Schematic (LVS) Check

• Connectivity Extraction: Physical extractor converts layout geometry (polygons) into netlist by recognizing devices (transistor gate/source/drain, capacitor plates, resistor paths).
• Device Identification: Gate poly overlaps diffusion → transistor. Parallel poly lines → capacitor. Meander metal → resistor (length/width ratio computed).
• Netlist Comparison: Extracted netlist from layout compared to schematic netlist. Checks: same devices, same connections, matching names/properties.
• LVS Failure Modes: Missing devices (layout missing diode), extra devices (parasitic transistor from poly leak-through), incorrect connectivity (net misnamed), device parameter mismatch (width differs).

Calibre and IC Validator Tools

• Calibre (Mentor): Industry-leading physical verification tool. DRC/LVS/PEX integrated platform. Supports tcl scripting for custom rule definition.
• IC Validator (Synopsys): Integrated into Synopsys design flow. Fast DRC turnaround (optimized for ultra-large designs >500M transistors).
• Foundry-Specific Rule Decks: Calibre rules written in Calibre Interactive Language (CIL). Different technology nodes, library cells require separate rule decks.
• Cloud/Distributed Verification: Large designs exceeding single-machine memory partitioned across compute clusters. Distributed verification reduces turnaround from hours to minutes.

Antenna Rule Check and ERC

• Antenna Effect: Metal accumulation during fabrication (poly etch process) charges floating poly/metal. Subsequent gate oxide breakdown occurs if charge exceeds device breakdown limit.
• Antenna Rule: Metal area ratio (accumulated metal to gate area) must be <100-1000 (technology-dependent). Violations indicate need for diffusion breaks or diode insertion.
• Diode Insertion: Parasitic diode bridges antenna net to substrate. Diode conducts accumulated charge harmlessly. EDA tools auto-insert diodes at violations.
• ERC (Electrical Rule Check): Checks unconnected nets (floating nodes), shorted supplies (VDD-GND short), undriven nodes. Catches connectivity errors missed by LVS.

Parasitic Extraction (RCX/PEX)

• Resistance Extraction: Metal line resistance = ρ × length / (width × thickness). Cross-coupling resistance between adjacent wires computed from layer geometry.
• Capacitance Extraction: Oxide capacitance (line-to-substrate), coupling capacitance (line-to-line), fringing capacitance (field lines at edges). 2D/3D field solvers compute C from geometry.
• SPICE Netlist Generation: Extracted RC/L values annotated as passive elements in detailed SPICE netlist. Used for post-layout timing/power simulation.
• Extraction Accuracy: Capacitance extraction uncertainty ~5-10% due to geometry approximation, process variations. Resistance extraction ~2% via resistivity tables.

Hierarchical Verification Flow

• Cell-Level Verification: Each macro/standard cell verified independently. Cell DRC/LVS clean before integration into larger blocks.
• Hierarchical DRC/LVS: Top-level design partitioned into subcells. Rules enforced at each hierarchy level (avoids repeated checking of deep hierarchies).
• Cross-Hierarchy Checks: Some violations require multi-level context. Example: antenna rule needs to account for multiple metal levels above gate.
• Incremental Verification: Changes to small regions re-verified only in affected windows. Avoids full-design re-check, reducing turnaround time.

Waiver Management

• Exception Handling: Some violations acceptable by design. Example: antenna violation at power-gating header transistor (intentional charge storage).
• Waiver Database: Documented exceptions recorded in waiver file. Each waiver includes location, reason, approval authority, sign-off date.
• Audit Trail: Waivers linked to design change requests. Enables traceability and prevents unauthorized exceptions creeping into production.
• Yield Impact: Waived rules monitored post-fab. If yield loss correlates with waiver location, rule reinstated and design revised.