Design-Technology Co-Optimization (DTCO) is the iterative methodology that simultaneously optimizes semiconductor process technology and circuit design rules to maximize performance, density, and yield at each new node — replacing the historically sequential approach where process engineers first defined rules and designers then worked within them. DTCO recognizes that the greatest gains at sub-10nm nodes come from jointly tuning patterning, cell architecture, routing rules, and device parameters as a unified system rather than independent silos.

Why DTCO Is Now Essential

• Traditional approach: Process team defines PDK → design team adapts → limited feedback loop → suboptimal PPA.
• DTCO approach: Process + design iterate together from day one → each technology choice is evaluated for circuit impact before being finalized.
• Driver: At 7nm and below, every design rule change (track count, contacted poly pitch, fin pitch) has disproportionate impact on cell area, power, and routability — these cannot be decoupled.

Key DTCO Metrics

DTCO Workflow

• Step 1 — Patterning exploration: Evaluate candidate CPP/fin pitch combos vs. lithography constraints.
• Step 2 — Cell architecture study: For each patterning option, estimate standard cell height (track count) and drive strength.
• Step 3 — SPICE extraction: Extract parasitics for each candidate → simulate ring oscillator, SRAM, critical paths.
• Step 4 — Routing analysis: Run place-and-route on benchmark circuits → measure congestion, wire length, via count.
• Step 5 — Yield modeling: Map defect density and pattern complexity to predicted yield → combine with PPA into score.
• Step 6 — Node selection: Choose technology parameters that maximize PPA × yield score.

STCO — System-Technology Co-Optimization

• Extends DTCO to the system level: includes chiplet partitioning, packaging, memory bandwidth, and thermal constraints.
• Example: Co-optimizing die-to-die interconnect (UCIe pitch, bandwidth) with compute die architecture.
• Used by Intel, TSMC, Samsung for 2nm-class nodes and advanced packaging decisions.

Tools and Infrastructure

DTCO Impact at Key Nodes

• 10nm: Track height reduced from 9T to 7.5T via DTCO — 15% area gain.
• 7nm: CPP scaled from 84nm to 57nm driven by cell area DTCO targets.
• 5nm: Back-end-of-line pitch reduction co-optimized with standard cell M0/M1 routing.
• 3nm/2nm: DTCO now includes nanosheet width, inner spacer, backside power rail, and fin-cut rules.

DTCO has become the central methodology for sustaining Moore's Law economics — by making process and design co-equal partners in node definition, it consistently unlocks 15–30% PPA improvements that neither team could achieve independently.