Dual damascene forms both trench (line) and via (vertical connection) in a single sequence, reducing process steps and cost compared to single damascene. Process flow: 1) Deposit dielectric stack, 2) pattern and etch via holes, 3) pattern and etch trenches (or reverse order), 4) deposit barrier/liner, 5) fill with metal, 6) CMP. Integration schemes: Via-first: Etch vias through full dielectric, then etch trenches to partial depth. Most common approach. Trench-first: Etch trenches first, then etch vias at bottom of trenches. Advantage over single damascene: One metal fill and one CMP step per interconnect level instead of two. Lower cost, better via-to-line interface (no CMP interface). Via-to-trench alignment: Critical that via is properly positioned within trench. Misalignment causes resistance increase or reliability failure. Etch challenges: Two different etch depths in same film stack. Requires etch stop layers or timed etch control. Etch stop: Thin SiCN or SiN layer between via and trench dielectric levels defines trench etch depth. Barrier coverage: Must coat both trench and via surfaces in one deposition. High-AR via requires IPVD or ALD. Fill challenge: Must fill high-AR via and wider trench simultaneously without voids. Scaling: Dual damascene standard for advanced interconnect from 130nm node onward.