Copper Damascene Interconnect Process is the metallization technique that forms copper wiring in pre-etched dielectric trenches (single damascene for vias, dual damascene for combined via+trench) โ using electroplating to fill the features and CMP to planarize, replacing aluminum RIE-based metallization at the 180 nm node due to copper's 40% lower resistivity (1.7 vs. 2.7 ฮผฮฉยทcm) and superior electromigration resistance, enabling the 10-15 metal layer interconnect stacks of modern processors.
Dual Damascene Process Flow
1. Dielectric Deposition: Low-k dielectric (SiCOH, k=2.5-3.0) deposited by PECVD. Ultra-low-k (k<2.5) uses porous varieties achieving k=2.0-2.4.
2. Patterning: Via-first approach: etch via holes through the full dielectric stack, then pattern and etch the trench (wider, shallower) in the upper portion. Or trench-first: reverse sequence. Both use multi-step lithography and etch.
3. Barrier/Seed Deposition:
- Barrier Layer: PVD TaN (1-3 nm) + Ta (1-3 nm). TaN prevents copper diffusion into the dielectric (copper is a fast diffuser that creates deep-level traps in silicon, killing transistors). Ta promotes copper adhesion.
- Copper Seed Layer: PVD copper (10-30 nm) provides the conductive layer for electroplating. Must continuously coat trench and via sidewalls โ conformality is critical in high aspect ratio features.
4. Copper Electroplating (ECP): The wafer is immersed in an acidified copper sulfate electrolyte. Electrochemical deposition fills features bottom-up using suppressor/accelerator/leveler additives that create differential deposition rates (faster at feature bottom, slower at top) to achieve void-free fill.
5. Anneal: Thermal anneal promotes copper grain growth (large grains โ lower resistance, better EM resistance).
6. CMP: Two-step CMP removes excess copper (step 1) and barrier (step 2) from field areas. Leaves planar surface for the next interconnect layer.
Scaling Challenges
- Resistivity Increase: At line widths below 30 nm, copper resistivity increases dramatically due to electron scattering at grain boundaries and surfaces. At 10 nm line width, effective resistivity can be 3-5ร bulk. This RC delay increase threatens to offset transistor speed gains.
- Barrier Scaling: The barrier+seed stack (6-10 nm) occupies a significant fraction of narrow lines, reducing the volume available for low-resistivity copper. At 3 nm node (M1 pitch ~20 nm, line width ~10 nm), the barrier may consume 30-60% of the cross-section.
- Alternative Metals: Ruthenium and cobalt are being evaluated for the narrowest lines โ they don't need barriers (no diffusion into dielectric), and their resistivity at narrow widths is competitive with copper-plus-barrier. Ruthenium's resistance to oxidation and higher melting point also improve reliability.
Electromigration in Copper
Copper atoms migrate along grain boundaries under high current density (electron wind force). Void formation causes resistance increase and eventually open circuits. Bamboo grain structure (grain boundaries perpendicular to current flow) provides the best EM resistance. Cobalt caps on copper lines improve EM lifetime by 10-100ร compared to conventional SiCN caps.
Copper Damascene is the interconnect technology that wires billions of transistors together โ the process that fills pre-patterned trenches with the lowest-resistivity practical conductor, creating the multi-layer metallic nervous system through which signals and power flow in every modern integrated circuit.