Channel strain engineering, embedded silicon-germanium (eSiGe) source/drain stressors, and dual contact etch stop liners (DSL / CESL) constitute the primary material-enhancement disciplines that boost transistor drive current without physical gate oxide thinning. In sub-90nm CMOS scaling, conventional geometric dimension shrinking encountered severe gate dielectric leakage and channel carrier velocity saturation. By intentionally introducing lattice strain into the silicon conduction channel, mechanical stress alters the cubic diamond crystal symmetry, lifting the degeneracy of the conduction and valence band energy states. Splitting the heavy-hole and light-hole valence sub-bands lowers carrier effective transport mass ($m^*$) and suppresses inter-band phonon scattering, enabling dramatic enhancements in hole mobility ($\mu_h > +200\%$) and electron mobility ($\mu_e > +60\%$) while scaling carrier injection velocity ($v_{\text{inj}}$) toward ballistic limits.

Embedded silicon-germanium source/drain stressors generate intense uniaxial compressive stress to double PMOS hole mobility. Because the natural diamond cubic lattice parameter of silicon-germanium ($a_{\text{SiGe}} = 5.431 + 0.20 x\ \text{Å}$) is larger than that of pure silicon ($a_{\text{Si}} = 5.431\ \text{Å}$), epitaxially growing pseudomorphic $\text{Si}_{1-x}\text{Ge}_x$ ($x \approx 0.25\text{--}0.40$) in recessed source/drain cavities exerts powerful longitudinal compressive stress ($\sigma_{xx} \approx -1.5\text{ to }-2.5\text{ GPa}$) into the adjacent silicon channel. To maximize stress transfer, fabs utilize anisotropic wet etching (tetramethylammonium hydroxide TMAH) to etch self-aligned sigma-shaped ($\Sigma$) source/drain cavities that bring the stressor material within five nanometers of the gate edge. Uniaxial compressive stress along the $\langle 110 \rangle$ channel transport direction induces an energy splitting ($\Delta E_v$) between the heavy-hole and light-hole valence sub-bands:

where $b$ is the shear deformation potential. This band splitting depopulates the heavy-hole band, confining conducting holes to the light-hole band where the effective transport mass ($m_h^*$) drops from $0.45 m_0$ to $0.18 m_0$, suppressing inter-subband optical phonon scattering and increasing PMOS hole mobility by more than $200\%$.

Tensile contact etch stop layers and stress memorization techniques boost NMOS electron mobility through conduction band valley repopulation. In NMOS transistors, electron mobility is enhanced by longitudinal tensile stress ($\sigma_{xx} > 0$). Foundries deploy Dual Stress Liners (DSL): a compressive silicon nitride film is deposited over PMOS regions, while a highly tensile PECVD silicon nitride ($\text{Si}_3\text{N}_4$) Contact Etch Stop Layer (CESL, intrinsic tensile stress $> 1.5\text{ GPa}$) caps NMOS transistors. The resulting uniaxial tensile stress splits the six-fold degenerate silicon conduction band valleys into two lower-energy perpendicular $\Delta_2$ valleys and four higher-energy in-plane $\Delta_4$ valleys ($\Delta E_c \approx 60\text{--}90\text{ meV}$). Electrons preferentially occupy the lower $\Delta_2$ sub-bands, where the longitudinal effective mass ($m_e^* = 0.19 m_0$) is significantly smaller than the transverse mass ($0.98 m_0$), while the energy gap suppresses intervalley phonon scattering, delivering electron mobility improvements exceeding $+60\%$.

The Stress Memorization Technique permanently locks plastic lattice deformation into the gate and channel during thermal spike annealing. In SMT integration, after NMOS source/drain extension implants, the poly-silicon gate electrode and source/drain regions are intentionally amorphized using high-dose neutral silicon ($\text{Si}^+$) or germanium ($\text{Ge}^+$) ion implantation. A temporary, highly tensile dielectric capping layer (such as stoichiometric $\text{Si}_3\text{N}_4$) is deposited across the wafer. During subsequent millisecond spike thermal annealing at $1050^\circ\text{C}$, the amorphous poly-silicon and silicon junctions recrystallize under intense mechanical confinement. When the sacrificial nitride capping layer is selectively stripped in hot phosphoric acid ($\text{H}_3\text{PO}_4$), the grain microstructure and channel lattice permanently retain (memorize) the tensile strain, yielding an independent $15\%\text{ to }25\%$ boost in NMOS saturation drive current ($I_{\text{Dsat}}$) with zero added topography.

Piezoresistive coupling and ballistic carrier injection velocity govern nanoscale transistor drive current enhancement. In nanoscale channels where channel length approaches the carrier mean free path ($L_g < 20\text{ nm}$), drive current is governed not merely by drift mobility, but by the ballistic injection velocity ($v_{\text{inj}}$) at the source virtual cathode:

By reducing the effective carrier conductivity mass ($m^*$) through uniaxial strain, the injection velocity increases by up to $45\%$, enabling modern FinFETs and GAA nanosheets to operate at supply voltages down to $0.7\text{V}$ while delivering saturation drive currents exceeding $1.5\text{ mA/}\mu\text{m}$.

st=>start: Patterned FinFET / Planar Transistor: dummy gate stack with thin offset sidewall spacers
sigma_etch=>operation: Anisotropic Sigma-Cavity Etch: wet TMAH etch creates self-aligned Σ-recesses in PMOS S/D
sige_epi=>operation: Selective eSiGe:B Epitaxy: CVD growth of Si0.65Ge0.35:B introduces > 2 GPa uniaxial compressive stress
smt_process=>operation: NMOS Stress Memorization (SMT): amorphize poly gate + cap with tensile Si3N4 + spike anneal
dsl_deposition=>operation: Dual Stress Liner (DSL): deposit tensile CESL on NMOS and compressive CESL on PMOS
pass=>end: Strained Transistor Signoff: PMOS mobility gain > 200% and NMOS mobility gain > 60% with Rc < 10^-9 ohm-cm2
st->sigma_etch->sige_epi->smt_process->dsl_deposition->pass

Delivering maximum switching speed and energy efficiency across advanced sub-3nm nodes requires evaluating carrier transport through a channel-strain-engineering-and-embedded-stressor lens. By uniting selective epitaxial embedded $\text{SiGe}$ growth, anisotropic sigma-cavity etching, dual stress liner contact etch stop layers, stress memorization recrystallization kinetics, and piezoresistive band splitting, transistor engineering teams surpass intrinsic bulk silicon limits. Mastering channel strain physics guarantees that high-performance AI processors, server microprocessors, and ultra-dense mobile chiplets deliver maximum drive currents, low operating voltages, and robust multi-year structural reliability.