eFuse and OTP Programming Circuits are non-volatile, one-time programmable memory elements integrated on-chip for permanent storage of calibration data, chip identification, security keys, and redundancy repair information — using irreversible physical changes (metal migration, oxide breakdown, or polysilicon melting) to encode binary data.

eFuse Technologies:

• Polysilicon eFuse: narrow polysilicon link melted by high current pulse (10-30 mA for 1-10 μs) — blown fuse increases resistance from ~100 Ω to >10 kΩ, detected by sense amplifier
• Metal eFuse: thin metal trace (typically copper or aluminum) electromigrated by sustained current — requires lower voltage but longer programming time (10-100 μs) than polysilicon fuses
• Oxide Anti-Fuse: thin gate oxide deliberately broken down by high voltage (>5V) — unprogrammed state is open circuit (>1 GΩ), programmed state creates conductive path (~1-10 kΩ) through damaged oxide
• ROM-Style Anti-Fuse: gate oxide anti-fuses organized in memory array with word-line/bit-line access — compatible with standard CMOS process without additional mask layers

Programming Circuits:

• Current Driver: large NMOS transistor (W > 10 μm) provides programming current — gated by enable logic with hardware/software interlock to prevent accidental programming
• Voltage Regulator: dedicated charge pump or LDO generates programming voltage (3.3-6.5V) from core supply — programming voltage must be precisely controlled to ensure reliable blow without damaging adjacent circuits
• Timing Control: precise pulse width control using on-chip timer — insufficient pulse width causes partial programming (marginal resistance), excessive pulse risks thermal damage to surrounding structures
• Verify After Program: each bit read back immediately after programming to confirm successful state change — failed bits can be re-programmed with higher current or longer pulse

Sense and Read Circuits:

• Resistance Sensing: sense amplifier compares fuse resistance against reference — typical threshold at 1-5 kΩ discriminates between blown (>10 kΩ) and intact (<500 Ω) fuses
• Read Margin: programmed and unprogrammed resistance distributions must maintain >10× separation across temperature (-40°C to 150°C) and aging — margin verification at extreme PVT corners during qualification
• Shadow Registers: fuse values loaded into volatile registers during boot sequence — eliminates need to sense fuses during normal operation, allowing fuse power supplies to be shut down after boot

Applications:

• Analog Trimming: DAC/ADC calibration coefficients, bandgap reference trim, clock frequency trim — 8-32 bits per trim parameter, programmed at wafer sort after measurement
• Chip ID and Security: unique die identification, encryption keys, secure boot hash — anti-fuse preferred for security applications due to difficulty of reverse engineering
• Memory Repair: defective row/column addresses stored in eFuse — repair mapping applied during memory initialization to redirect accesses from defective to redundant elements

eFuse and OTP circuits represent the permanent configuration layer of modern SoCs — enabling post-fabrication customization, silicon-specific calibration, and hardware root-of-trust that would be impossible with purely mask-programmed approaches.