Electrical Test Methods are the comprehensive suite of measurements that verify electrical functionality and performance of semiconductor devices — ranging from simple continuity tests to complex functional validation, using automated probe stations and testers to measure billions of transistors per wafer, identifying defective die, binning devices by performance grade, and providing the yield data that drives manufacturing improvement with test times from milliseconds to minutes per die.

Wafer-Level Parametric Testing:

• Test Structures: dedicated test structures placed in scribe lines or test die; includes resistors, capacitors, transistors, and interconnect chains; measures fundamental electrical parameters without requiring functional circuits
• Sheet Resistance: four-point probe measures sheet resistance of doped silicon, silicides, and metal films; van der Pauw structures eliminate contact resistance errors; target ±5% uniformity across wafer; monitors doping and metal deposition processes
• Capacitance-Voltage (CV): measures MOS capacitor C-V curves; extracts oxide thickness, doping concentration, interface trap density, and flatband voltage; critical for gate oxide and high-k dielectric characterization
• Transistor I-V Curves: measures drain current vs gate voltage (Id-Vg) and drain voltage (Id-Vd); extracts threshold voltage, transconductance, subthreshold slope, and leakage current; validates transistor performance before functional testing

Wafer Probe Testing:

• Probe Card Technology: array of probe needles contacts die pads; cantilever probes for peripheral pads, vertical probes for area-array pads; probe pitch down to 40μm for advanced packages; FormFactor and Technoprobe supply probe cards
• Automated Test Equipment (ATE): Advantest T2000 and Teradyne UltraFLEX systems provide pattern generation, timing control, and measurement capability; test speeds up to 6.4 Gb/s per pin; 1024-2048 test channels for parallel testing
• Test Flow: wafer loaded onto prober chuck; die aligned under probe card; probes descend to contact pads (overdrive 50-100μm ensures good contact); test patterns executed; results logged; probes lift; stage steps to next die
• Throughput: simple tests (continuity, leakage) complete in 10-50ms per die; functional tests require 100ms-1s per die; parallel testing of multiple die (4-16 die simultaneously) increases throughput; target 100-300 wafers per day per prober

Functional Testing:

• Test Patterns: digital patterns exercise logic functions; memory tests use march algorithms (write/read sequences) to detect stuck-at faults, coupling faults, and retention failures; analog tests measure DC parameters and AC performance
• At-Speed Testing: tests devices at operating frequency (1-5 GHz); detects timing failures invisible at slow speeds; requires high-speed ATE and probe cards; critical for high-performance processors and memories
• Scan Testing: design-for-test (DFT) structures enable internal node access; scan chains shift test patterns into flip-flops; combinational logic evaluated; results shifted out; achieves >95% fault coverage with manageable pattern count
• Built-In Self-Test (BIST): on-chip test pattern generators and response analyzers; reduces ATE complexity and test time; memory BIST standard in modern designs; logic BIST emerging for complex SoCs

Defect Detection:

• Stuck-At Faults: signal permanently at logic 0 or 1; caused by opens, shorts, or gate oxide defects; detected by applying opposite logic value and checking response
• Bridging Faults: unintended connections between signals; caused by metal shorts or particle contamination; detected by driving opposite values on bridged nets and checking for conflicts
• Delay Faults: excessive propagation delay causes timing failures; caused by resistive opens, weak transistors, or interconnect RC; detected by at-speed testing with timing-critical patterns
• Parametric Failures: device operates but outside specifications (speed, power, voltage); caused by process variations; detected by measuring performance parameters and comparing to limits

Inking and Binning:

• Ink Marking: failing die marked with ink dot; prevents packaging of known-bad die; automated inking systems integrated with probers; ink removed before dicing if die will be retested
• Bin Classification: passing die classified by performance grade; speed bins (e.g., 3.0 GHz, 2.8 GHz, 2.5 GHz), voltage bins (1.0V, 1.1V, 1.2V), and functionality bins (full-featured vs reduced-feature); enables product differentiation and revenue optimization
• Wafer Map: visual representation of die pass/fail status; spatial patterns indicate systematic yield issues; clustered failures suggest equipment problems; edge failures indicate handling issues
• Yield Calculation: die yield = (passing die) / (total testable die); excludes edge die and test structures; typical yields 50-90% depending on product maturity and complexity

Advanced Test Techniques:

• Adaptive Testing: adjusts test flow based on early results; skips remaining tests if critical failure detected; reduces test time by 20-40% without sacrificing quality
• Outlier Screening: identifies marginally passing die likely to fail in the field; uses multivariate analysis of parametric measurements; screens out reliability risks; reduces field failure rate by 50-80%
• Correlation Analysis: correlates electrical test results with inline metrology and inspection data; identifies process-test relationships; guides yield improvement efforts
• Machine Learning Classification: neural networks predict die yield from inline data; enables early dispositioning and process adjustment; achieves 85-90% prediction accuracy

Test Data Analysis:

• Shmoo Plots: 2D maps of pass/fail vs two parameters (voltage vs frequency, voltage vs temperature); visualizes operating margins; identifies process sensitivities
• Parametric Distributions: histograms of measured parameters (Vt, Idsat, leakage); monitors process centering and variation; detects process shifts and excursions
• Spatial Analysis: maps parametric values across wafer; identifies systematic patterns; correlates with process tool signatures; guides root cause analysis
• Temporal Trends: tracks yield and parametric values over time; detects equipment drift and material lot effects; triggers corrective actions

Test Cost Optimization:

• Test Time Reduction: parallel testing, adaptive testing, and test pattern optimization reduce test time by 50-70%; test cost proportional to test time
• Multi-Site Testing: tests 4-16 die simultaneously; requires independent test channels per die; amortizes prober overhead across multiple die
• Test Coverage Optimization: balances fault coverage vs test time; focuses on high-probability faults; accepts 95% coverage instead of 99% if cost savings justify
• Retest Strategies: retests failing die to eliminate false failures from probe contact issues; typically 5-10% of failures pass on retest; balances yield loss vs retest cost

Electrical test methods are the final verification that semiconductor manufacturing has succeeded — measuring the electrical reality of billions of transistors, separating functional devices from defective ones, and providing the quantitative feedback that closes the loop from manufacturing process to product performance, ensuring that only working chips reach customers.