Electromigration (EM) Analysis is the reliability verification process that ensures metal interconnects can sustain their operating current densities over the chip's lifetime without failure due to atomic migration caused by high current flow — requiring careful analysis of average and RMS current, wire widths, via counts, and temperature to prevent open circuits or shorts that would cause catastrophic chip failure after months or years of operation.

Electromigration Physics:

• Atomic Migration Mechanism: high current density (electrons flowing through metal) transfers momentum to metal atoms through collisions; atoms gradually migrate in the direction of electron flow, creating voids (opens) at the cathode end and hillocks (extrusions) at the anode end
• Black's Equation: MTTF = A·j^(-n)·exp(Ea/kT) where j is current density, T is temperature, Ea is activation energy (~0.7-0.9 eV for copper), n is current density exponent (1-2); doubling current density reduces lifetime by 2-4×; 10°C temperature increase reduces lifetime by ~2×
• Failure Modes: void formation increases resistance until open circuit occurs; hillocks can cause shorts to adjacent wires; typical EM failure criterion is 10% resistance increase or complete open; target MTTF is 10-20 years at operating conditions
• Material Dependence: copper has better EM resistance than aluminum (higher activation energy); copper with barrier layers (TaN, Ta) and capping layers (CoWP, SiCN) further improves EM lifetime; advanced nodes use selective capping for critical nets

EM Design Rules:

• DC Current Limits: maximum allowed DC current density typically 0.5-1.5 mA/μm wire width depending on metal layer, temperature, and required lifetime; lower layers (M1-M3) have tighter limits due to smaller grain size and higher temperature
• AC Current Limits: AC current causes bidirectional atomic migration with partial self-healing; AC limits are 1.5-3× higher than DC limits; RMS current used for AC analysis: I_rms = sqrt(Σ(I_i²·duty_i))
• Via Current Limits: vias are EM-critical due to high current density in small cross-section; single via typically limited to 0.2-0.5 mA; via arrays (multiple vias in parallel) required for high-current nets; redundant vias improve reliability
• Width and Length Rules: minimum wire width for given current; maximum wire length without intermediate vias (reservoir effect); wider wires have lower current density but also different grain structure affecting EM; foundry provides lookup tables mapping current to required width

EM Analysis Flow:

• Current Extraction: gate-level simulation with realistic activity vectors extracts average and RMS current for every net; power nets analyzed separately using static and dynamic IR drop analysis; clock nets require special attention due to 100% activity factor
• Temperature Mapping: chip temperature varies spatially (hotspots near high-power blocks); EM analysis uses temperature-aware current limits; thermal analysis (Ansys RedHawk-SC, Cadence Celsius) provides temperature map; 20°C hotspot requires 1.4× wider wires for same MTTF
• EM Checking: Calibre PERC, Synopsys IC Validator, and Cadence Quantus compare extracted currents against foundry EM rules; violations reported as wire width insufficient or via count insufficient; critical violations must be fixed before tapeout
• Immortality Condition: for short wires with blocking boundaries (vias at both ends), Blech length criterion determines if EM can occur; if wire length < Blech length (~10-50μm depending on current density), atomic migration is balanced by back-stress and no EM failure occurs

EM-Aware Design Techniques:

• Power Grid Sizing: power and ground nets carry highest currents; sized with 2-3× margin beyond minimum EM requirements; use top metal layers (lowest resistance, best EM properties) for power distribution
• Clock Tree EM: clock buffers and nets have 100% activity; clock tree synthesis must consider EM constraints when sizing buffers and routing clock nets; typically requires 1.5-2× wider wires than signal nets at same current
• Signal Net Optimization: high-activity signal nets (data buses, control signals) may violate EM rules; solutions include wire widening, via doubling, buffer insertion (splits current), or activity reduction through clock gating
• Via Redundancy: design rules often require redundant vias for all power nets and high-current signal nets; double-via or via array insertion automated during routing; improves both EM reliability and yield (manufacturing defect tolerance)

Advanced Node Challenges:

• Scaling Impact: as wire dimensions shrink, current density increases for the same current; 7nm/5nm nodes have tighter EM limits and require more aggressive design margins; via resistance increases faster than wire resistance, making vias the primary EM bottleneck
• Self-Heating: Joule heating in narrow wires raises local temperature above ambient; self-heating effect becomes significant at 7nm/5nm, requiring coupled electro-thermal EM analysis; can reduce effective MTTF by 20-40%
• Statistical EM: process variations cause wire width and via resistance variations affecting EM; statistical EM analysis (similar to statistical timing) ensures EM reliability under process corners; typically adds 10-15% margin to deterministic limits
• Package-Level EM: C4 bumps and package interconnects also subject to EM; co-design of on-chip PDN and package power delivery ensures no EM violations across the entire path from voltage regulator to transistor

Electromigration analysis is the reliability verification that prevents latent failures in the field — EM violations may not cause immediate failure at manufacturing test but lead to premature chip death after months of operation, making thorough EM analysis and design margin essential for product reliability and customer trust.