Electromigration-Aware Routing and EM Signoff is the physical design methodology that ensures no metal wire or via in the chip carries current density exceeding the technology's electromigration (EM) lifetime limits — preventing the gradual atomic migration of metal atoms under sustained current flow that creates voids (opens) and hillocks (shorts), with EM being the primary long-term reliability failure mechanism for copper interconnects and requiring analysis of every net in the design during signoff.

Electromigration Physics

• Current flows through Cu wire → momentum transfer from electrons to Cu atoms.
• Cu atoms gradually migrate in direction of electron flow (opposite to current).
• Upstream: Atoms leave → void forms → resistance increases → eventually open circuit.
• Downstream: Atoms accumulate → hillock forms → can short to adjacent wire.
• Time to failure: MTF ∝ (1/J^n) × exp(Ea/kT), where J=current density, n≈1-2.

EM Design Rules

EM Analysis Flow

1. Extract: Get parasitic R/C for every net from layout. 2. Simulate: Run circuit simulation to get current waveform through every wire segment. 3. Calculate: Compute RMS, average, and peak current density for each segment. 4. Compare: Check against technology EM limits (DC, AC, peak). 5. Report: Flag violations with wire location, current, and limit. 6. Fix: Widen wire, add parallel routes, or reduce current.

DC vs. AC EM

• Signal nets: Usually AC (rise/fall transitions) → more relaxed EM limits.
• Power nets (VDD/VSS): DC current → strictest EM limits → widest wires needed.
• Clock nets: AC but very high switching activity → moderate EM concern.

EM Fix Strategies

Power Grid EM

• Power grid carries maximum DC current → most EM-critical region.
• Analysis: IR drop tool computes current in every power stripe and via.
• Common fix: Add power straps, increase strap width, add decap cells.
• Via EM: Often the weakest link → via arrays (2×, 4×) required at power connections.

EM in Advanced Nodes

• Thinner wires: Lower cross-section → higher current density for same current.
• Cu grain boundary: More grain boundaries in narrow wires → faster EM.
• Barrier-free metals (Ru, Mo): Different EM characteristics → new EM models needed.
• Cobalt cap: On Cu surface → blocks Cu surface diffusion → improves EM lifetime 2-5×.

Electromigration-aware routing is the reliability engineering discipline that ensures chips survive their intended lifetime — with EM analysis required on every wire and via in designs containing billions of connections, automated EM signoff tools are essential for catching the handful of high-current-density violations among millions of nets that would otherwise cause field failures years after deployment, making EM one of the most compute-intensive but non-negotiable steps in the tapeout signoff flow.