Electromigration (EM) in Chip Design is the gradual displacement of metal atoms in interconnect wires caused by momentum transfer from conducting electrons — leading to void formation (opens) or hillock growth (shorts) that cause chip failure after prolonged operation, requiring designers to enforce strict current density limits on every wire and via in the layout.

EM Mechanism

• High current density → electron "wind" pushes metal atoms in direction of current flow.
• Atoms deplete at cathode end (upstream) → void forms → wire resistance increases → eventual open circuit.
• Atoms accumulate at anode end (downstream) → hillock/extrusion → potential short to adjacent wire.
• Time to failure: $TTF \propto \frac{1}{J^n} \cdot e^{E_a/kT}$ (Black's equation).
• J = current density, n ≈ 1-2, Ea = activation energy (~0.7-0.9 eV for Cu).

Current Density Limits

• AC signals have lower EM risk — atoms oscillate back and forth.
• DC (power/ground) has highest EM risk — sustained directional current.

Blech Length Effect

• For short wires: Back-stress from atom accumulation at anode opposes electron wind.
• Below Blech length (typically 5-20 μm): Back-stress completely balances EM force → immortal wire (no EM failure).
• $J \cdot L < (J \cdot L)_{critical}$ → wire is EM-immortal.
• Implication: Short signal wires are generally EM-safe; long power lines are the concern.

EM-Aware Design Practices

• Power grid sizing: Wider/thicker power stripes to reduce current density.
• Via arrays: Multiple vias in parallel at power connections — reduce per-via current.
• Metal slotting: Long wide wires slotted to reduce stress migration.
• EM signoff: Tools (RedHawk, Voltus) check every wire and via against foundry EM rules.

EM Signoff Flow

1. Extract power grid and signal nets. 2. Compute current density for every wire segment and via. 3. Compare against foundry EM limits (temperature-dependent). 4. Flag violations → designer widens wires or adds vias. 5. Iterate until zero EM violations.

Electromigration analysis is a mandatory signoff check for every production chip — a single EM violation that passes to silicon means the chip will fail in the field, making EM signoff as critical as timing signoff for product reliability.