Strain/Stressor Engineering in CMOS is the deliberate introduction of mechanical stress into the transistor channel to enhance carrier mobility — where compressive stress improves hole mobility (PMOS) by 50-80% and tensile stress improves electron mobility (NMOS) by 30-50%, making strain engineering one of the most impactful performance boosters in the CMOS toolkit, continuously adapted from planar to FinFET to nanosheet architectures.

Physics of Strain-Enhanced Mobility

Mechanical stress alters the silicon crystal's band structure. For electrons (NMOS), biaxial or uniaxial tensile stress along the channel direction splits the conduction band valleys, populating the low-effective-mass valleys and reducing intervalley scattering — increasing mobility. For holes (PMOS), compressive stress along the channel lifts the heavy-hole/light-hole degeneracy, reducing the effective mass and suppressing scattering — increasing mobility. The mobility enhancement is proportional to stress magnitude up to ~2 GPa.

Stressor Techniques

• Embedded SiGe Source/Drain (eSiGe): Epitaxially grown Si₁₋ₓGeₓ (x=0.25-0.40) in the source/drain regions of PMOS. The larger Ge lattice constant creates compressive stress in the adjacent Si channel. Introduced at 90nm node, still used at all nodes. The stress magnitude increases with Ge content and proximity to the channel.

• Embedded SiC Source/Drain (eSiC): Si₁₋ᵧCᵧ (y~0.01-0.02) in NMOS source/drain creates tensile channel stress. The smaller C lattice constant pulls the channel into tension. Lower stress magnitude than eSiGe due to limited C solubility.

• Stress Memorization Technique (SMT): Deposit a high-stress silicon nitride liner over the gate before source/drain activation anneal. During the anneal, the stress is "memorized" in the gate and channel regions through plastic deformation and defect rearrangement. The nitride liner can then be removed — the stress persists.

• Contact Etch Stop Layer (CESL) Stress: Deposit compressive SiN over PMOS and tensile SiN over NMOS as the contact etch stop layer. Dual-stress liner (DSL) technique requires selected removal of one stress type from the opposite device type.

Strain in FinFET Architecture

FinFETs complicate strain engineering because the fin geometry constrains stress transfer. The 3D fin shape allows stress along the fin (longitudinal) but partially relaxes stress in the transverse and vertical directions. Embedded SiGe in FinFET source/drain creates less uniaxial channel stress per unit Ge content compared to planar. Higher Ge concentrations (up to 50-65%) compensate.

Strain in Gate-All-Around Nanosheets

Nanosheet transistors introduce new strain challenges and opportunities. The nanosheet channel is nearly free-standing, connected to source/drain epitaxy at both ends. Channel stress depends on the epitaxial growth conditions of the nanosheet, the inner spacer geometry, and the SiGe source/drain composition. Cladding SiGe layers around Si nanosheets can introduce strain directly during epitaxial growth.

Strain Engineering is the performance multiplier that has delivered 30-80% mobility improvement at every technology node since 90nm — continuously reinvented for each new transistor architecture while remaining fundamentally rooted in the quantum mechanical relationship between crystal stress and carrier effective mass.