Performance per watt normalizes useful computing performance by electrical power. It is a central comparison for thermally constrained mobile devices, dense datacenters, and accelerators where raw speed cannot exceed cooling, delivery, battery, or operating-cost limits. The numerator may be tokens/s, images/s, jobs/s, FLOPS, or qualified goodput; the denominator may be chip, board, node, rack, or wall power. Only aligned boundaries support comparison. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. State workload, precision, quality, latency, batch, utilization, software, power mode, sustained duration, numerator and denominator boundaries, and uncertainty.

Architecture, quantitative model, and operating behavior. A performance-power scatter plot shows absolute capacity and draw; rays from the origin are iso-efficiency lines. A point farther up at the same power or farther left at the same performance is better, but system constraints may value capacity or latency differently. Voltage and frequency typically show diminishing performance with rising power near the top of the curve. Specialization, quantization, locality, sparsity, and batching can move the curve; idle and fixed system power make low utilization inefficient. Peak TOPS/W, sustained application goodput/W, energy-delay product, energy-delay squared, perf per rack watt, and performance per dollar capture different priorities. TOPS/W across different operation definitions is not architecture-neutral. Useful analysis separates arithmetic, memory hierarchy, interconnect, storage, control, and queuing. It counts operations and bytes at each boundary, identifies dependencies and reuse, estimates ideal ceilings, and then uses counters and traces to explain the gap between the model and measurement. Ratios without a clearly named numerator and denominator invite invalid comparisons. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints.

Implementation, hardware mapping, and bottlenecks. Measure synchronized performance and power at multiple caps, keep quality and SLO fixed, include necessary host/memory/network overhead, find the efficient frontier, and select operating points from rack or battery constraints. ASICs can eliminate programmability overhead, GPUs provide flexible high utilization across workloads, FPGAs exploit custom pipelines at lower frequency, CPUs handle irregular control, and NPUs integrate efficient inference. Process and memory technology strongly affect each. Comparing H100, TPU, MI300X, or custom ASIC headline TOPS without aligned precision, sparsity, workload, power boundary, software maturity, and availability is invalid; exact rankings are workload-specific. Begin with a correct reference and representative shapes. Profile end to end, classify the dominant resource, inspect kernel and system timelines, change one bottleneck at a time, and remeasure because optimization moves pressure elsewhere. Tiling, fusion, batching, vectorization, layout, precision, compression, overlap, prefetch, sharding, and algorithm choice are useful only when they reduce the limiting resource. The execution path spans registers, local SRAM and caches, HBM or GDDR, host DRAM, PCIe or coherent links, scale-up fabric, network, and storage. Compute units consume tensors only when compilers and kernels issue enough independent work and the hierarchy supplies operands. Package wiring, memory stacks, clocks, voltage, thermal headroom, and power delivery determine sustained limits. Frequent mistakes include quoting peak instead of achieved rates, omitting data conversion and transfer, measuring a cached toy input, timing asynchronous work without synchronization, mixing decimal and binary units, ignoring warmup or throttling, changing precision or quality, averaging away tails, and optimizing a component that is not on the critical path.

Measurement, validation, and engineering controls. Use the same model, dataset, quality, batch and latency target; tune each platform fairly; measure external power; report sustained goodput and confidence intervals; and disclose unsupported operations or fallbacks. Qualified work/s/W, joules/result, latency, throughput, utilization, memory, power cap, temperature, rack density, cost, and carbon intensity matter. Power-cap sweeps reveal whether the device sits beyond its efficiency knee; component accounting shows whether host, memory, network, or cooling dominates. Verification combines analytical bounds, microbenchmarks, hardware counters, kernel timelines, end-to-end traces, scaling sweeps, sensitivity to batch and shape, cold and warm runs, long-duration thermal tests, correctness comparisons, fault and congestion tests, and independent reproduction. Roofline and queueing models guide diagnosis but must be calibrated against the deployed machine. Benchmark code, datasets, model and compiler artifacts, drivers, firmware, topology, clock and power settings, environment, commands, raw samples, counter traces, and analysis notebooks remain versioned. Continuous tests detect regressions in quality, latency, throughput, bandwidth, memory, power, and cost, with thresholds chosen from variance rather than a single run. Published comparisons disclose configuration, exclusions, tuning effort, measurement boundary, quality criteria, and uncertainty. Energy and carbon claims distinguish chip, IT, and facility boundaries and avoid extrapolating one benchmark to all workloads. Owners review regressions and retain evidence sufficient to reproduce decisions.

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Selection and system-level application. Choose from the measured Pareto frontier for the actual deployment; favor ASIC specialization for stable volume, GPUs for broad programmable use, FPGAs for tailored pipelines, and CPUs for control-heavy tasks. Datacenter training and inference, mobile and edge AI, robotics, HPC, networking, and embedded signal processing use performance per watt. The metric emerges from workload, software, architecture, process, memory, package, board, cooling, utilization, and facility boundary. Optimization is a system exercise across algorithms, precision, kernels, compiler, runtime, accelerator, memory, interconnect, scheduler, serving policy, cooling, and facility limits. Removing one ceiling often exposes another, so architecture decisions should optimize time and energy to a useful result rather than an isolated metric. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.