Home Knowledge Base Mathematical Modeling of Epitaxy in Semiconductor Front-End Processing (FEP)

Mathematical Modeling of Epitaxy in Semiconductor Front-End Processing (FEP)

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  <text x="380" y="32" fill="#e6edf3" font-size="20" font-weight="700" text-anchor="middle">Epitaxial Growth Mechanics — Lattice Matching &amp; Strain Engineering</text>
  <text x="380" y="52" fill="#8b98a5" font-size="12" text-anchor="middle">Pseudomorphic Lattice Distortion, Critical Thickness Thresholds &amp; Selective Growth (SEG)</text>

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    <text x="172.5" y="24" fill="#60a5fa" font-size="13" font-weight="700" text-anchor="middle">1. Lattice Matching &amp; Strain States</text>
    
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      <text x="157.5" y="18" fill="#60a5fa" font-size="10.5" font-weight="700" text-anchor="middle">A. Homoepitaxy (Si on Si — Matched Lattice)</text>
      
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      <text x="157.5" y="118" fill="#8b98a5" font-size="8.5" text-anchor="middle">a_film = a_sub | Zero Strain (ε = 0) | Perfect Crystal Continuity</text>
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      <text x="157.5" y="18" fill="#fbbf24" font-size="10.5" font-weight="700" text-anchor="middle">B. Heteroepitaxy (Compressive SiGe on Si)</text>
      
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      <text x="157.5" y="114" fill="#fca5a5" font-size="8.5" font-weight="700" text-anchor="middle">Compressive Strain: a_parallel = a_sub, a_perp &gt; a_sub</text>
      <text x="157.5" y="128" fill="#8b98a5" font-size="8" text-anchor="middle">Coherent Pseudomorphic Growth below Critical Thickness h_c</text>
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    <text x="172.5" y="24" fill="#34d399" font-size="13" font-weight="700" text-anchor="middle">2. Selective Epitaxy (SEG) in FinFET/GAA</text>

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      <text x="157.5" y="18" fill="#3fb950" font-size="11" font-weight="700" text-anchor="middle">Embedded SiGe Source/Drain (Uniaxial Strain)</text>

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      <text x="157.5" y="118" fill="#34d399" font-size="8" font-weight="700" text-anchor="middle">Boosts pMOS Hole Mobility &gt; 50% via Longitudinal Strain</text>
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      <text x="157.5" y="18" fill="#e6edf3" font-size="10.5" font-weight="700" text-anchor="middle">Growth Kinetics &amp; HCl Chemical Selectivity</text>
      
      <text x="25" y="42" fill="#8b98a5" font-size="8.5">• <tspan fill="#38bdf8" font-weight="700">Gas Phase Precursors</tspan>: DCS (SiH₂Cl₂) + GeH₄ + HCl + B₂H₆</text>
      <text x="25" y="60" fill="#8b98a5" font-size="8.5">• <tspan fill="#fbbf24" font-weight="700">HCl Role</tspan>: Etches amorphous nuclei on SiO₂/SiN mask</text>
      <text x="25" y="78" fill="#8b98a5" font-size="8.5">• <tspan fill="#34d399" font-weight="700">Faceting</tspan>: {111} planes have slowest growth rate</text>
      
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      <text x="157.5" y="105" fill="#60a5fa" font-size="8.5" font-weight="700" text-anchor="middle">Atomic-Level Doping: In-situ Boron / Phosphorus Insertion</text>
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  <text x="380" y="430" fill="#fbbf24" font-size="9.5" font-weight="700" text-anchor="middle">Misfit Strain ε = (a_film - a_sub)/a_sub | Pseudomorphic growth below Critical Thickness h_c drives Channel Mobility</text>

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  <text x="380" y="458" fill="#6b7684" font-size="11" text-anchor="middle">Foundational FEOL process for GAA nanosheets, SiGe pMOS channels &amp; InP/GaAs RF photonics</text>
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1. Overview

Epitaxy is a critical Front-End Process (FEP) step where crystalline films are grown on crystalline substrates with precise control of:

Mathematical modeling enables:

1.1 Types of Epitaxy

1.2 Epitaxy Methods

2. Fundamental Thermodynamic Framework

2.1 Driving Force for Growth

The supersaturation provides the thermodynamic driving force:

$$\Delta \mu = k_B T \ln\left(\frac{P}{P_{eq}}\right)$$

Where:

2.2 Free Energy of Mixing (Multi-component Systems)

For systems like SiGe alloys:

$$\Delta G_{mix} = RT\left(x \ln x + (1-x) \ln(1-x)\right) + \Omega x(1-x)$$

Where:

2.3 Gibbs Free Energy of Formation

$$\Delta G = \Delta H - T\Delta S$$

For spontaneous growth: $\Delta G < 0$

3. Growth Rate Kinetics

3.1 The Two-Regime Model

Epitaxial growth rate is governed by two competing mechanisms:

Overall growth rate equation:

$$G = \frac{k_s \cdot h_g \cdot C_g}{k_s + h_g}$$

Where:

3.2 Temperature Dependence

The surface reaction rate follows Arrhenius behavior:

$$k_s = A \exp\left(-\frac{E_a}{k_B T}\right)$$

Where:

3.3 Growth Rate Regimes

Temperature RegimeLimiting FactorGrowth Rate ExpressionTemperature Dependence
Low TSurface reaction$G \approx k_s \cdot C_g$Strong (exponential)
High TMass transport$G \approx h_g \cdot C_g$Weak (~$T^{1.5-2}$)

3.4 Boundary Layer Analysis

For horizontal CVD reactors, the boundary layer thickness evolves as:

$$\delta(x) = \sqrt{\frac{ u \cdot x}{v_{\infty}}}$$

Where:

u$ = kinematic viscosity (m²/s)

The mass transfer coefficient:

$$h_g = \frac{D_{gas}}{\delta}$$

Where $D_{gas}$ is the gas-phase diffusion coefficient.

4. Surface Kinetics: BCF Theory

The Burton-Cabrera-Frank (BCF) model describes atomic-scale growth mechanisms.

4.1 Surface Diffusion Equation

$$D_s \nabla^2 n_s - \frac{n_s - n_{eq}}{\tau_s} + J_{ads} = 0$$

Where:

4.2 Characteristic Diffusion Length

$$\lambda_s = \sqrt{D_s \tau_s}$$

This parameter determines the growth mode:

4.3 Surface Diffusion Coefficient

$$D_s = D_0 \exp\left(-\frac{E_m}{k_B T}\right)$$

Where:

4.4 Step Velocity

$$v_{step} = \frac{2 D_s (n_s - n_{eq})}{\lambda_s} \tanh\left(\frac{L}{2\lambda_s}\right)$$

Where $L$ is the inter-step spacing (terrace width).

4.5 Growth Rate from Step Flow

$$G = \frac{v_{step} \cdot h_{step}}{L}$$

Where $h_{step}$ is the step height (monolayer thickness).

5. Heteroepitaxy and Strain Modeling

5.1 Lattice Mismatch

$$f = \frac{a_{film} - a_{substrate}}{a_{substrate}}$$

Where:

Example values:

SystemLattice Mismatch
Si₀.₇Ge₀.₃ on Si~1.2%
Ge on Si~4.2%
GaAs on Si~4.0%
InAs on GaAs~7.2%
GaN on Sapphire~16%

5.2 Strain Components

For biaxial strain in (001) films:

$$\varepsilon_{xx} = \varepsilon_{yy} = \varepsilon_{\parallel} = \frac{a_s - a_f}{a_f} \approx -f$$
$$\varepsilon_{zz} = \varepsilon_{\perp} = -\frac{2C_{12}}{C_{11}} \varepsilon_{\parallel}$$

Where $C_{11}$ and $C_{12}$ are elastic constants.

5.3 Elastic Energy

For a coherently strained film:

$$E_{elastic} = \frac{2G(1+ u)}{1- u} f^2 h = M f^2 h$$

Where:

u$ = Poisson's ratio

u)}{1- u}$

5.4 Critical Thickness (Matthews-Blakeslee)

$$h_c = \frac{b}{8\pi f(1+ u)} \left[\ln\left(\frac{h_c}{b}\right) + 1\right]$$

Where:

u$ = Poisson's ratio

5.5 People-Bean Approximation (for SiGe)

Empirical formula:

$$h_c \approx \frac{0.55}{f^2} \text{ (nm, with } f \text{ as a decimal)}$$

Or equivalently:

$$h_c \approx \frac{5500}{x^2} \text{ (nm, for Si}_{1-x}\text{Ge}_x\text{)}$$

5.6 Threading Dislocation Density

Above critical thickness, dislocation density evolves:

$$\rho_{TD}(h) = \rho_0 \exp\left(-\frac{h}{h_0}\right) + \rho_{\infty}$$

Where:

6. Reactor-Scale Modeling

6.1 Coupled Transport Equations

6.1.1 Momentum Conservation (Navier-Stokes)

$$\rho\left(\frac{\partial \mathbf{v}}{\partial t} + \mathbf{v} \cdot \nabla \mathbf{v}\right) = -\nabla p + \mu \nabla^2 \mathbf{v} + \rho \mathbf{g}$$

Where:

6.1.2 Continuity Equation

$$\frac{\partial \rho}{\partial t} + \nabla \cdot (\rho \mathbf{v}) = 0$$

6.1.3 Species Transport

$$\frac{\partial C_i}{\partial t} + \mathbf{v} \cdot \nabla C_i = D_i \nabla^2 C_i + R_i$$

Where:

6.1.4 Energy Conservation

$$\rho c_p \left(\frac{\partial T}{\partial t} + \mathbf{v} \cdot \nabla T\right) = k \nabla^2 T + \sum_j \Delta H_j r_j$$

Where:

6.2 Silicon CVD Chemistry

6.2.1 From Silane (SiH₄)

Gas phase decomposition:

$$\text{SiH}_4 \xrightarrow{k_1} \text{SiH}_2 + \text{H}_2$$

Surface reaction:

$$\text{SiH}_2(g) + * \xrightarrow{k_2} \text{Si}(s) + \text{H}_2(g)$$

Where $*$ denotes a surface site.

6.2.2 From Dichlorosilane (DCS)

$$\text{SiH}_2\text{Cl}_2 \rightarrow \text{SiCl}_2 + \text{H}_2$$
$$\text{SiCl}_2 + \text{H}_2 \rightarrow \text{Si}(s) + 2\text{HCl}$$

6.2.3 Rate Law

$$r_{dep} = k_2 P_{SiH_2} (1 - \theta)$$

Where:

6.3 Dimensionless Numbers

NumberDefinitionPhysical Meaning
Reynolds$Re = \frac{\rho v L}{\mu}$Inertia vs. viscous forces
Prandtl$Pr = \frac{\mu c_p}{k}$Momentum vs. thermal diffusivity
Schmidt$Sc = \frac{\mu}{\rho D}$Momentum vs. mass diffusivity
Damköhler$Da = \frac{k_s L}{D}$Reaction rate vs. diffusion rate
Grashof

u^2}$ | Buoyancy vs. viscous forces |

7. Selective Epitaxial Growth (SEG) Modeling

7.1 Overview

In SEG, growth occurs on exposed Si but not on dielectric (SiO₂/Si₃N₄).

7.2 Loading Effect Model

$$G_{local} = G_0 \left(1 + \alpha \cdot \frac{A_{mask}}{A_{Si}}\right)$$

Where:

7.3 Pattern-Dependent Growth

Sources of non-uniformity:

7.4 Selectivity Condition

For selective growth on Si vs. oxide:

$$r_{deposition,Si} > 0 \quad \text{and} \quad r_{deposition,oxide} < r_{etching,oxide}$$

Achieved by adding HCl:

$$\text{Si}(nuclei) + 2\text{HCl} \rightarrow \text{SiCl}_2 + \text{H}_2$$

Nuclei on oxide are etched before they can grow, maintaining selectivity.

7.5 Faceting Model

Growth rate depends on crystallographic orientation:

$$G_{(hkl)} = G_0 \cdot f(hkl) \cdot \exp\left(-\frac{E_{a,(hkl)}}{k_B T}\right)$$

Typical growth rate hierarchy:

$$G_{(100)} > G_{(110)} > G_{(111)}$$

8. Dopant Incorporation

8.1 Segregation Coefficient

Equilibrium segregation coefficient:

$$k_0 = \frac{C_{solid}}{C_{liquid/gas}}$$

Effective segregation coefficient:

$$k_{eff} = \frac{k_0}{k_0 + (1-k_0)\exp\left(-\frac{G\delta}{D_l}\right)}$$

Where:

8.2 Dopant Concentration in Film

$$C_{film} = k_{eff} \cdot C_{gas}$$

8.3 Dopant Profile Abruptness

The transition width is limited by:

$$\Delta z_{transition} \approx \sqrt{\lambda_{seg}^2 + L_D^2}$$

8.4 Common Dopants for Si Epitaxy

DopantTypePrecursorSegregation Behavior
Bp-typeB₂H₆, BCl₃Low segregation
Pn-typePH₃, PCl₃Moderate segregation
Asn-typeAsH₃Strong segregation
Sbn-typeSbH₃Very strong segregation

9. Atomistic Simulation Methods

9.1 Kinetic Monte Carlo (KMC)

9.1.1 Event Rates

Each atomic event has a rate following Arrhenius:

$$\Gamma_i = u_0 \exp\left(-\frac{E_i}{k_B T}\right)$$

Where:

u_0$ = attempt frequency (~10¹²-10¹³ s⁻¹)

9.1.2 Events Modeled

u_0 \exp(-E_{des}/k_B T)$

u_0 \exp(-E_m/k_B T)$

9.1.3 Time Advancement

$$\Delta t = -\frac{\ln(r)}{\Gamma_{total}} = -\frac{\ln(r)}{\sum_i \Gamma_i}$$

Where $r$ is a uniform random number in $(0,1]$.

9.2 Density Functional Theory (DFT)

Provides input parameters for KMC:

Kohn-Sham equation:

$$\left[-\frac{\hbar^2}{2m}\nabla^2 + V_{eff}(\mathbf{r})\right]\psi_i(\mathbf{r}) = \varepsilon_i \psi_i(\mathbf{r})$$

9.3 Molecular Dynamics (MD)

Newton's equations:

$$m_i \frac{d^2 \mathbf{r}_i}{dt^2} = -\nabla_i U(\mathbf{r}_1, \mathbf{r}_2, ..., \mathbf{r}_N)$$

Where $U$ is the interatomic potential (e.g., Stillinger-Weber, Tersoff for Si).

10. Nucleation Theory

10.1 Classical Nucleation Theory (CNT)

10.1.1 Gibbs Free Energy Change

$$\Delta G(r) = -\frac{4}{3}\pi r^3 \cdot \frac{\Delta \mu}{\Omega} + 4\pi r^2 \gamma$$

Where:

10.1.2 Critical Nucleus Radius

Setting $\frac{d(\Delta G)}{dr} = 0$:

$$r^* = \frac{2\gamma \Omega}{\Delta \mu}$$

10.1.3 Free Energy Barrier

$$\Delta G^* = \frac{16 \pi \gamma^3 \Omega^2}{3 (\Delta \mu)^2}$$

10.1.4 Nucleation Rate

$$J = Z \beta^* N_s \exp\left(-\frac{\Delta G^*}{k_B T}\right)$$

Where:

10.2 Growth Modes

ModeSurface Energy ConditionGrowth BehaviorExample
Frank-van der Merwe$\gamma_s \geq \gamma_f + \gamma_{int}$Layer-by-layer (2D)Si on Si
Volmer-Weber$\gamma_s < \gamma_f + \gamma_{int}$Island (3D)Metals on oxides
Stranski-KrastanovIntermediate2D then 3D islandsInAs/GaAs QDs

10.3 2D Nucleation

Critical island size (atoms):

$$i^* = \frac{\pi \gamma_{step}^2 \Omega}{(\Delta \mu)^2 k_B T}$$

11. TCAD Process Simulation

11.1 Overview

Tools: Synopsys Sentaurus Process, Silvaco Victory Process

11.2 Diffusion-Reaction System

$$\frac{\partial C_i}{\partial t} = \nabla \cdot (D_i \nabla C_i - \mu_i C_i \nabla \phi) + G_i - R_i$$

Where:

11.3 Point Defect Dynamics

Vacancy concentration:

$$\frac{\partial C_V}{\partial t} = D_V \nabla^2 C_V + G_V - k_{IV} C_I C_V$$

Interstitial concentration:

$$\frac{\partial C_I}{\partial t} = D_I \nabla^2 C_I + G_I - k_{IV} C_I C_V$$

Where $k_{IV}$ is the recombination rate constant.

11.4 Stress Evolution

Equilibrium equation:

$$\nabla \cdot \boldsymbol{\sigma} = 0$$

Constitutive relation:

$$\boldsymbol{\sigma} = \mathbf{C} : (\boldsymbol{\varepsilon} - \boldsymbol{\varepsilon}^{thermal} - \boldsymbol{\varepsilon}^{intrinsic})$$

Where:

11.5 Level Set Method for Interface Tracking

$$\frac{\partial \phi}{\partial t} + v_n |\nabla \phi| = 0$$

Where:

12. Advanced Topics

12.1 Atomic Layer Epitaxy (ALE) / Atomic Layer Deposition (ALD)

Self-limiting surface reactions modeled as Langmuir kinetics:

$$\theta = \frac{K \cdot P \cdot t}{1 + K \cdot P \cdot t} \rightarrow 1 \quad \text{as } t \rightarrow \infty$$

Growth per cycle (GPC):

$$GPC = \theta_{sat} \cdot d_{monolayer}$$

Typical GPC values: 0.5-1.5 Å/cycle

12.2 III-V on Silicon Integration

Challenges and models:

u}$

12.3 Quantum Dot Formation (Stranski-Krastanov)

Critical thickness for islanding:

$$h_{SK} \approx \frac{\gamma}{M f^2}$$

Island density:

$$n_{island} \propto \exp\left(-\frac{E_{island}}{k_B T}\right) \cdot F^{1/3}$$

Where $F$ is the deposition flux.

12.4 Machine Learning in Epitaxy Modeling

Physics-Informed Neural Networks (PINNs):

$$\mathcal{L}_{total} = \mathcal{L}_{data} + \lambda_{PDE}\mathcal{L}_{physics} + \lambda_{BC}\mathcal{L}_{boundary}$$

Where:

Applications:

13. Key Equations

PhenomenonKey EquationPrimary Parameters
Growth rate (dual regime)$G = \frac{k_s h_g C_g}{k_s + h_g}$Temperature, pressure, flow
Surface diffusion length$\lambda_s = \sqrt{D_s \tau_s}$Temperature
Lattice mismatch$f = \frac{a_f - a_s}{a_s}$Material system
Critical thickness

u)}\left[\ln\frac{h_c}{b}+1\right]$ | Mismatch, Burgers vector |

Elastic strain energy$E = M f^2 h$Mismatch, thickness, modulus
Nucleation rate$J \propto \exp(-\Delta G^*/k_BT)$Supersaturation, surface energy
Species transport$\frac{\partial C}{\partial t} + \mathbf{v}\cdot\nabla C = D\nabla^2 C + R$Diffusivity, velocity, reactions
KMC event rate

u_0 \exp(-E_a/k_BT)$ | Activation energy, temperature |

Physical Constants

ConstantSymbolValue
Boltzmann constant$k_B$$1.38 \times 10^{-23}$ J/K
Gas constant$R$8.314 J/mol$\cdot$K
Planck constant$h$$6.63 \times 10^{-34}$ J$\cdot$s
Electron charge$e$$1.60 \times 10^{-19}$ C
Si lattice constant$a_{Si}$5.431 Å
Ge lattice constant$a_{Ge}$5.658 Å
GaAs lattice constant$a_{GaAs}$5.653 Å

Single-Wafer Epi Reactor Cross-Section. The dominant reactor architecture for advanced logic epi is the cold-wall, single-wafer, lamp-heated chamber — a design that can ramp from 400$^\circ$C to 1150$^\circ$C in under 30 seconds and cool back in 60 seconds, enabling the tight thermal budgets that GAA nanosheet superlattices demand. Gas enters through a horizontal injector, flows across the rotating wafer in a laminar sheet, and exits through an exhaust port on the opposite side. The wafer sits on a SiC-coated graphite susceptor heated by banks of tungsten-halogen lamps above and below the quartz chamber walls.

Single-Wafer Epi Reactor (Cold-Wall, Lamp-Heated) Applied Materials Centura / ASM Epsilon architecture — ramp 400→1150°C in 30 s Quartz Chamber (transparent to IR) Upper Lamp Bank (W-halogen, 50–100 kW total) Lower Lamp Bank Gas In SiHCl₃/H₂ or DCS/GeH₄ Exhaust HCl + unreacted SiC-coated Graphite Susceptor (rotating, 20–50 rpm) 300 mm Wafer Wafer temp: 500–1150°C (pyrometer controlled ±1°C) Chamber walls stay cold (quartz transparent to lamp IR) Boundary layer (1–5 mm) — mass transport limited at high T Pyrometer Cold-wall design: only the susceptor and wafer are hot — minimizes parasitic deposition on chamber surfaces Rapid thermal ramp enables multi-step epi (pre-bake → nucleation → growth → cool) in one recipe Applied Materials Centura Epi (55% market) | ASM Epsilon 3200 (30%) | ~3B USD market (2023)

CVD Chemistry and Thermal Budget. The epi process is a chemical vapor deposition where the substrate temperature determines whether growth is limited by surface kinetics (low T) or by gas-phase mass transport (high T). At 1050–1150$^\circ$C with trichlorosilane (SiHCl$_3$/H$_2$), the growth rate reaches 0.5–4 $\mu$m/min in the mass-transport regime — fast enough for substrate epi layers of 2–10 $\mu$m in under 5 minutes. At 500–700$^\circ$C with dichlorosilane (SiH$_2$Cl$_2$/GeH$_4$/HCl), growth drops to 5–30 nm/min but enables selective epitaxy: HCl etches polycrystalline nuclei on oxide and nitride surfaces while leaving single-crystal growth on exposed silicon intact, achieving selectivity exceeding 100:1. The thermal budget constraint is absolute — at 900$^\circ$C, Ge interdiffusion reaches 1.9 nm/hour ($D = 10^{-17}$ cm$^2$/s), which smears a 5 nm SiGe/Si interface into a graded transition. This is why GAA nanosheet superlattice epi operates at 500–650$^\circ$C despite the 10$\times$ lower growth rate: interface abruptness ($<$1 nm transition width) matters more than throughput for the 2 nm node.

GAA Nanosheet Superlattice — The Defining Epi Challenge of the 2 nm Node. Gate-all-around transistors require a perfectly periodic Si/SiGe superlattice grown by epitaxy: alternating layers of Si (5–7 nm, future channel) and Si$_{0.7}$Ge$_{0.3}$ (8–12 nm, sacrificial, later removed by selective etch). A typical 2 nm node stack has 4–8 pairs, totaling 60–120 nm, with each layer controlled to $\pm$0.3 nm thickness and Ge composition held at $\pm$1 atomic percent uniformity across 300 mm. The growth sequence alternates SiH$_4$ (Si layers) and SiH$_2$Cl$_2$/GeH$_4$ (SiGe layers) at 500–650$^\circ$C with H$_2$ carrier gas at 10–80 Torr. Interface abruptness demands gas switching in $<$2 seconds (purge between layers) and minimal thermal exposure after growth. Any interdiffusion wider than 1 nm at the Si/SiGe boundary creates a graded composition that shifts the selective etch endpoint by 0.5–2 nm — enough to fail the channel thickness specification.

GAA Nanosheet Si/SiGe Superlattice (Epi Growth) 4–8 alternating pairs, ±0.3 nm per layer, grown at 500–650°C Si Substrate SiGe (10 nm, 30% Ge) — sacrificial Si (6 nm) — channel SiGe (10 nm, 30% Ge) Si (6 nm) — channel SiGe (10 nm, 30% Ge) Si (6 nm) — channel SiGe (10 nm, 30% Ge) Si (6 nm) — channel (top) SiN hard mask Si channels: 5–7 nm thick ±0.3 nm tolerance Future GAA channel SiGe sacrificial: 8–12 nm thick 30% Ge ±1 at% Removed by selective etch to release sheets Interface Requirement Ge transition: <1 nm Gas switch: <2 seconds Temp: 500–650°C max After fin patterning, selective etch removes SiGe → releases 4 stacked Si nanosheets → gate wraps all sides Intel 20A, Samsung 2nm, TSMC N2 all use this superlattice epi architecture (2024–2025)

Selective Epitaxial Growth (SEG) for Raised Source/Drain. Since the 45 nm node, PMOS transistors use compressive-strained SiGe grown selectively in etched recesses adjacent to the gate. The epi fills only the crystalline Si surface while HCl in the gas stream continuously etches any polycrystalline nuclei that form on surrounding SiO$_2$ or Si$_3$N$_4$ — achieving greater than 100:1 selectivity without a mask. At 650$^\circ$C with SiH$_2$Cl$_2$/GeH$_4$/HCl/H$_2$ at 10 Torr, growth proceeds at 10–20 nm/min with Ge content of 25–50 atomic percent. The resulting SiGe exerts uniaxial compressive strain on the Si channel between the source/drain regions, increasing hole mobility by 50–100% — the performance boost that kept planar CMOS scaling alive from 90 nm through 22 nm before FinFET took over.

Selective Epi Growth: SiGe Source/Drain Strain Engineering SiGe grows only on exposed Si — HCl etches nuclei on oxide/nitride (selectivity >100:1) Si Substrate Gate HfO₂/TiN Spacer SiGe S/D 30–50% Ge SiGe S/D 30–50% Ge Si channel (compressive strain) ← Compressive strain → hole mobility +50–100% SiO₂ No growth SiO₂ No growth Process: 650°C | SiH₂Cl₂ + GeH₄ + HCl + H₂ | 10 Torr | 10–20 nm/min HCl selectivity mechanism: etches poly nuclei on oxide, preserves epitaxial crystal on Si Used at every node from 45 nm (Intel) through FinFET and GAA — billions of transistors per wafer

EPI Chamber Cross-Section — Hardware Subsystems. The single-wafer epi chamber integrates thermal, chemical, mechanical, and optical subsystems into a compact cold-wall reactor optimized for rapid thermal cycling. Unlike plasma etch chambers that require RF generators and vacuum in the millitorr regime, the epi reactor operates at 10–760 Torr with purely thermal activation — the lamp bank replaces the plasma as the energy source for breaking precursor bonds on the wafer surface.

EPI Chamber Cross-Section — Hardware Subsystems Cold-wall lamp-heated CVD: only the susceptor reaches process temperature Quartz tube Upper Lamp Array (40–60 kW, 11 zones) Lower Lamp Array (20–40 kW, 7 zones) SiC-coated Graphite Susceptor 300 mm Wafer (500–1150°C) Motor 20–50 rpm Gas Inject MFC Exhaust Throttle + Scrub P P Multi-point pyrometry (±1°C) — controls lamp power per zone Stagnant boundary layer (1–5 mm) Process Volume: H₂ carrier + precursor at 10–760 Torr Laminar flow, Re < 100, no turbulence Chamber cost: 2–4M USD | Susceptor life: 5,000+ wafers | Quartz tube: 10,000+ wafers | Lamp: 2,000 hours No plasma, no RF, no vacuum pump below 1 Torr — purely thermal CVD activation

EPI Chamber Control Schematic — Temperature, Gas, and Thickness Feedback. The epi reactor is a multi-input, multi-output control system where lamp power (11+ independent zones), gas flow (4–8 MFC channels), susceptor rotation, and chamber pressure must all coordinate to deliver ±0.3 nm thickness and ±1 at% composition uniformity. Unlike etch where RF power is the primary control variable, epi control is dominated by temperature — because growth rate has an Arrhenius dependence with activation energy 1.5–3.0 eV, meaning a 1°C error at 600°C changes the rate by 0.3–0.5%.

EPI Chamber Control Schematic Temperature-dominated control: Arrhenius rate means ±1°C → ±0.3–0.5% rate change Recipe T, flow, time per step Lamp Power (kW) 11 Zones Wafer T MFCs (4–8 ch) Manifold Chamber Throttle Valve Pump 10–760 Torr Sensors Pyrometer (T) Reflectometer (thickness) Baratron (P) FTIR (composition) Slip detection Haze monitor All real-time, wafer-by-wafer Feedback: pyrometer → lamp PID | reflectometer → gas switch | Baratron → throttle Result: ±0.3 nm thickness | ±1 at% Ge | ±1°C uniformity across 300 mm, wafer-to-wafer 3σ < 0.5% Multi-zone lamp PID runs at 100 Hz; gas switching completes in <2 s for superlattice interfaces In-situ reflectometry provides real-time thickness — closes the loop without post-metrology

EPI Chamber Process Environment — No Plasma, Pure Thermal Activation. Unlike etch and PECVD chambers that use plasma to dissociate precursors, the epi reactor relies entirely on thermal energy at the wafer surface to decompose gas molecules. At 1050°C, SiHCl$_3$ pyrolyzes on the Si surface with an activation energy of 1.8 eV — the surface temperature provides sufficient energy to break the Si–H and Si–Cl bonds, releasing HCl and incorporating Si into the crystal lattice. At 600°C for selective SiGe, the lower activation energy of GeH$_4$ decomposition (0.9 eV) enables Ge incorporation while SiH$_2$Cl$_2$ decomposition (1.5 eV) proceeds more slowly — this differential sets the Ge fraction. The absence of plasma means no ion bombardment, no radiation damage, no charging — enabling perfect crystalline growth with defect densities below $10^2$ cm$^{-2}$.

EPI Process: Thermal Activation (No Plasma) Surface temperature provides all activation energy — defect density <100 cm⁻² Growth Rate vs Temperature 1/T (1000/K) → ln(Rate) 1150°C 900°C 650°C 500°C Mass transport 0.5–4 µm/min Surface kinetics 5–30 nm/min E_a = 1.5–3.0 eV Transition ~900°C Precursor Activation Energies SiHCl₃ (TCS): E_a = 1.8 eV, T > 1000°C Rate: 0.5–4 µm/min SiH₂Cl₂ (DCS): E_a = 1.5 eV, T = 600–900°C Rate: 10–50 nm/min GeH₄ (Germane): E_a = 0.9 eV, T = 500–700°C Ge fraction set by GeH₄/DCS ratio SiH₄ (Silane): E_a = 1.2 eV, T = 500–650°C Si layers in superlattice Lower E_a precursors enable lower temperature → sharper interfaces → better GAA nanosheets Trade-off: lower T = slower rate = lower throughput (5 WPH for superlattice vs 10 WPH for substrate epi) No plasma damage: defect density <100 cm⁻² | No charging | Perfect lattice continuity

EPI Process Metrics — What the Fab Measures. The epi process is qualified by six metrics that collectively determine whether the grown layer meets transistor specifications: (1) thickness uniformity ($\pm$0.5% across 300 mm, $\pm$0.3 nm for nanosheets), (2) composition uniformity (Ge $\pm$1 at% for SiGe), (3) defect density ($<$0.1 defects/cm$^2$ for substrate epi, $<$100/cm$^2$ for selective), (4) resistivity uniformity ($\pm$3% for doped layers), (5) surface roughness ($<$0.1 nm RMS by AFM), and (6) interface abruptness ($<$1 nm Ge transition for superlattice). Metrology uses spectroscopic ellipsometry (thickness/composition), four-point probe (resistivity), haze inspection (particles), X-ray diffraction (strain/composition), and cross-section TEM (interface verification). Every wafer gets inline ellipsometry; TEM sampling runs at 1 per lot (25 wafers) for process monitoring.

EPI Typical Process — Step-by-Step Sequence. A representative selective SiGe source/drain epi process on a 300 mm wafer runs the following sequence in a single chamber recipe lasting 4–8 minutes total: (1) Load wafer onto susceptor at 400°C, purge chamber with H$_2$ at 100 Torr (30 s). (2) Ramp to 800°C in H$_2$ for pre-bake surface clean — removes native oxide via H$_2$ reduction (60 s). (3) Cool to 650°C stabilization temperature (30 s). (4) Introduce SiH$_2$Cl$_2$ + GeH$_4$ + HCl + B$_2$H$_6$ (dopant) at 10 Torr — selective growth at 15 nm/min, Ge = 35%, boron $2 \times 10^{20}$ cm$^{-3}$ (120–240 s for 30–60 nm). (5) Purge all precursors, ramp to 700°C for 10 s anneal (optional, for dopant activation). (6) Cool to 400°C, unload (60 s). Total thermal budget: 650°C peak for 4 minutes — compatible with HKMG gate-last integration. Chamber conditions between wafers: 30 s H$_2$ purge + lamp idle at 400°C. Throughput: 5–8 WPH per chamber, 20–32 WPH on a 4-chamber cluster.

EPI Typical Productivity Improvements (2015–2024). The epi equipment industry has delivered consistent productivity gains through hardware and process innovation, reducing cost-per-wafer-pass by approximately 8% per year: (1) Multi-zone lamp PID (11→16 zones) reduced center-to-edge temperature non-uniformity from $\pm$3°C to $\pm$1°C, eliminating the need for rework and increasing first-pass yield from 92% to 99%. (2) Fast gas switching valves ($<$1 s actuation vs $<$5 s legacy) enabled superlattice epi without dedicated purge steps, cutting cycle time by 15%. (3) Higher lamp power density (100 kW peak vs 60 kW) enabled 30 s ramps instead of 60 s — directly adding 30 s throughput per wafer. (4) In-situ reflectometry closed the thickness loop wafer-by-wafer, reducing the metrology burden and enabling APC (advanced process control) that compensates for susceptor aging across 5,000-wafer campaigns. (5) Selective epi without the pre-clean step (replacing ex-situ HF dip with in-situ H$_2$ bake at 800°C) eliminated a wet-bench tool from the flow, saving 2 minutes of queue time and one cross-contamination risk. (6) Cluster tool integration (epi + pre-clean + cool-down in vacuum) removed atmosphere exposure between steps, reducing interface oxygen from $10^{12}$ to $<10^{10}$ atoms/cm$^2$. Net result: cost per epi wafer-pass dropped from $\sim$45 USD (2015) to $\sim$28 USD (2024) while the process specification tightened 3$\times$ — the definition of a mature equipment learning curve.

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