Epitaxial Wafer Preparation — Epitaxial wafer preparation involves growing a high-quality single-crystal silicon layer on a polished silicon substrate, providing the precisely controlled surface material in which advanced CMOS transistors are fabricated with superior crystal quality, dopant uniformity, and defect density compared to bulk wafer surfaces.

Epitaxial Growth Fundamentals — Silicon epitaxy is performed by chemical vapor deposition in specialized reactor systems:

• Precursor gases including SiH4 (silane), SiH2Cl2 (dichlorosilane), SiHCl3 (trichlorosilane), and SiCl4 (silicon tetrachloride) provide silicon atoms for crystal growth
• Growth temperature ranges from 600°C for silane-based low-temperature epitaxy to 1150°C for chlorosilane-based high-temperature processes
• Growth rate is controlled by temperature, precursor partial pressure, and gas flow dynamics, typically ranging from 0.1 to 5 μm/min
• Dopant incorporation is achieved by adding PH3 (phosphine), B2H6 (diborane), or AsH3 (arsine) to the process gas mixture during growth
• Single-wafer reactors with lamp-heated chambers provide the temperature uniformity and rapid thermal response needed for advanced epitaxial processes

Epitaxial Layer Specifications — Critical parameters define the quality requirements for epitaxial wafers:

• Thickness uniformity within ±1–2% across the wafer is required to ensure consistent device characteristics
• Resistivity uniformity within ±3–5% is achieved through precise dopant gas flow control and temperature management
• Crystal defect density including stacking faults, dislocations, and epitaxial spikes must be minimized to below 0.1 defects/cm²
• Surface roughness below 0.1nm RMS is maintained through optimized growth conditions and in-situ surface preparation
• Autodoping suppression prevents unintentional dopant transfer from the heavily doped substrate into the epitaxial layer through gas phase or solid-state transport

Pre-Epitaxial Surface Preparation — Substrate surface quality directly determines epitaxial layer quality:

• RCA clean sequence removes organic, metallic, and particulate contamination from the wafer surface before loading into the reactor
• HF last clean creates a hydrogen-terminated silicon surface that resists native oxide formation during wafer transfer
• In-situ hydrogen bake at 1100–1150°C removes residual native oxide and surface contaminants immediately before epitaxial growth
• Reduced pressure baking at lower temperatures minimizes dopant redistribution in the substrate while achieving adequate surface preparation
• Surface reconstruction during the hydrogen bake creates the atomically smooth surface required for defect-free epitaxial nucleation

Advanced Epitaxial Applications — Beyond basic substrate preparation, epitaxy serves multiple specialized functions in CMOS:

• Lightly doped epitaxy on heavily doped substrates provides the low-defect active device layer while the substrate serves as a ground plane or gettering sink
• SiGe epitaxy for PMOS source/drain stressors and SiGe channel devices requires precise germanium composition and strain control
• SiC epitaxy for NMOS tensile stress applications demands careful carbon incorporation without precipitate formation
• Selective epitaxial growth (SEG) deposits silicon or SiGe only on exposed silicon surfaces within oxide or nitride windows
• Multilayer epitaxial stacks for gate-all-around nanosheet transistors alternate Si and SiGe layers with atomic-level thickness precision

Epitaxial wafer preparation is a foundational process in advanced CMOS manufacturing, providing the high-quality crystalline starting material that enables the precise dopant profiles, low defect densities, and strain engineering capabilities required by leading-edge transistor architectures.