**Homoepitaxy and heteroepitaxy solve different problems.** Homoepitaxy grows nominally the same semiconductor on itself, such as silicon on silicon or SiC on SiC, to create a controlled-purity, controlled-doping device layer. Heteroepitaxy grows a different composition or material, such as SiGe on Si, GaN on SiC, or a III–V quantum well, to engineer band structure, strain, confinement, polarization, or optical response. Heteroepitaxy must also manage lattice, thermal-expansion, chemistry, polarity, and interface mismatch. **Choose the platform backward from the required crystal and interface.** Silicon vapor-phase epitaxy prioritizes native-oxide removal, dopant profile, autodoping, thickness, slip, haze, and wafer-scale uniformity. Embedded SiGe or Si:C source/drain layers add selectivity, pattern loading, facets, substitutional composition, and strain transfer. III–V MOCVD and MBE add alloy ordering, precursor or beam-flux control, V/III ratio, polarity, and abrupt quantum interfaces. Wide-bandgap homoepitaxy adds polytype replication, basal-plane and threading defects, and very thick drift-layer control. | Epitaxy platform | Crystal source and control style | Best fit | Dominant integration burden | Decisive qualification evidence | |---|---|---|---|---| | Silicon/SiGe thermal CVD or VPE | hydride/chlorosilane surface chemistry in H₂ or inert carrier | blanket Si, SiGe, raised/recessed device structures | seed cleanliness, autodoping, loading, selectivity, facets and slip | thickness/composition maps, XRD/Raman, defects, SIMS, Rs and cross-sections | | III–V MOCVD | metal-organic group-III sources plus hydride/group-V chemistry | LEDs, lasers, RF and electronic heterostructures | precursor parasitics, carbon/H impurities, V/III response, thermal and polarity mismatch | HRXRD, PL, AFM, TEM, Hall, composition and wafer uniformity | | Molecular beam epitaxy | independently controlled elemental or molecular beams in UHV | quantum wells, superlattices, abrupt research/device stacks | low throughput, source drift, shutter/transient control and background contamination | RHEED, flux calibration, HRXRD, TEM, PL and transport | | SiC or GaN homo/hetero CVD | high-temperature step-flow and precursor chemistry | power/RF drift layers and buffers | polytype, step bunching, wafer bow, extended defects and thick-film uniformity | defect maps, PL/cathodoluminescence, morphology, doping and breakdown monitors | | Remote/plasma-assisted or low-temperature epi | activated radicals with reduced thermal budget | temperature-sensitive interfaces and emerging materials | plasma damage, incomplete surface cleaning, non-epi nucleation and contamination | interface TEM, recombination/lifetime, phase maps, damage and electrical tests | **The seed surface is the first process step.** Epitaxy cannot copy a lattice through uncontrolled native oxide, carbon, metal contamination, polymer residue, or a damaged amorphous layer. Wet cleans, HF-last preparation, vapor treatments, in-situ bake, hydrogen bake, halogen chemistry, plasma, or atomic-hydrogen treatment may be used according to the material and thermal budget. Each route trades oxide removal, roughening, impurity, step morphology, and device damage. **“Oxide-free” needs direct or functional evidence.** Contact angle and queue time are useful process indicators but do not prove an atomically clean buried interface. XPS or other surface methods, in-situ diffraction, cross-sectional TEM, carrier lifetime, interface recombination, contact resistance, and defect decoration provide different evidence. The correct set depends on whether the interface is a transport path, a junction, or only a seed. **Queue time is part of epitaxy.** A hydrogen-terminated silicon surface reoxidizes and adsorbs carbon or water; a III–V surface reconstructs or loses volatile species; a cleaned SiC surface can acquire contamination. Ambient, humidity, load-lock pumpdown, wafer temperature, outgassing, and time to precursor exposure must be controlled. A perfect clean followed by an uncontrolled wait is not a controlled interface. **Thermal desorption has an integration cost.** Higher-temperature bake can remove oxide or smooth a surface, but it can also cause dopant diffusion, recess rounding, gate-stack damage, silicon loss, slip, or dewetting of nearby films. Lower-temperature chemistry can preserve the structure but may leave oxygen, halogen, hydrogen, or plasma damage. Qualify the complete clean-plus-growth sequence on the patterned stack. **Crystal orientation and miscut set the step template.** A nominal (100), (111), or (0001) wafer contains terraces and steps determined by orientation, miscut magnitude/direction, polishing, etch, and thermal treatment. Step density affects incorporation and the competition between step-flow and terrace nucleation. Miscut can suppress one defect mode while increasing step bunching or anisotropic morphology. **Step-flow growth is a kinetic regime, not a guarantee of perfection.** Adsorbed species diffuse across terraces and incorporate preferentially at ledges and kink sites. The balance among arrival flux, diffusion length, step spacing, desorption, and incorporation determines whether steps advance smoothly, bunch, meander, or are overtaken by two-dimensional islands. Temperature or flux changes can move the surface between these modes. **Two-dimensional nucleation competes with step capture.** When supersaturation is high, diffusion length is short, or terraces are wide, stable islands form away from existing steps. Island coalescence can increase roughness and create boundaries or stacking defects. The relevant threshold depends on orientation, surface reconstruction, chemistry, and step density; it cannot be reduced to one universal temperature. **Three-dimensional islanding may be thermodynamic or kinetic.** In a strained heteroepitaxial system, accumulated elastic energy can favor islands; in another process, poor wetting, contamination, high supersaturation, or local temperature variation can produce similar morphology. AFM shapes alone do not identify the mechanism. Combine composition, strain, thickness evolution, interface evidence, and process perturbations. **Growth rate has reaction and transport contributions.** In a surface-reaction-sensitive regime, temperature and termination strongly affect incorporation. In a transport-sensitive regime, boundary-layer delivery, depletion, pressure, flow, rotation, and wafer loading dominate. The reciprocal-resistance picture is useful conceptually, but real reactors add multiple precursors, reversible reactions, gas-phase chemistry, and facet-dependent kinetics. **A flat rate versus temperature does not prove pure transport limitation.** Precursor depletion, desorption, etching, surface coverage, and compensating thermal fields can flatten the observed response. Measure rate against temperature, partial pressure, flow, rotation, loading, and wall state while monitoring morphology and composition. Apparent rate matching can hide a different surface state. **Precursor choice changes both growth and etch chemistry.** Silicon epitaxy can use silane, disilane, dichlorosilane, trichlorosilane, silicon tetrachloride, or related sources. Chlorinated species can suppress non-epi deposition and modify morphology, but introduce HCl/chloride, moisture sensitivity, corrosion, and exhaust deposits. Higher silanes lower activation in some windows but can raise gas-phase reaction and delivery challenges. **Hydrogen is often chemically active.** It serves as carrier, influences surface termination, assists oxide removal at temperature, changes precursor decomposition, and participates in etching or passivation. Replacing H₂ with inert carrier changes more than thermal conductivity. Purity, moisture, oxygen, flow, pressure, and safety infrastructure are part of the epi process. **For SiGe, composition and rate are coupled.** Germane or higher germanes interact with silicon precursor chemistry, temperature, surface termination, strain, and dopants. Germanium incorporation can change surface segregation, growth rate, roughness, facet development, and critical thickness. A gas-flow ratio is not a universal calibration of solid composition. **For compound semiconductors, stoichiometry is surface-mediated.** MOCVD group-III precursor decomposition, group-V supply, carrier gas, reactor pressure, and parasitic gas-phase reactions determine what reaches the surface. MBE beam-equivalent pressure or flux calibration, source temperature, cracker state, shutter timing, and reconstruction play corresponding roles. The commanded V/III ratio is not automatically the incorporated atomic ratio. **Lattice mismatch creates coherent strain before it creates relaxation.** A thin layer can elastically adopt the in-plane lattice spacing of the seed, with compensating out-of-plane distortion. The stored elastic energy grows with thickness and mismatch. Composition, elastic anisotropy, orientation, temperature, and existing defects determine the strain state. **Critical thickness is a model-dependent transition, not a single material constant.** Equilibrium force-balance models and kinetic/metastable models predict different thresholds. Dislocations need sources and mobility; a layer may remain metastably coherent beyond an equilibrium estimate or relax below an expected threshold if defects are available. State the model, growth temperature, thickness definition, composition profile, and detection limit. **Relaxation produces a defect network.** Misfit dislocations accommodate lattice mismatch near the interface; threading segments propagate toward the surface and interact, multiply, bend, or annihilate. Pileups and crosshatch morphology can create spatially nonuniform strain and device variability. Relaxation percentage alone does not describe the residual threading-defect risk. **Thermal-expansion mismatch acts during cooldown.** A layer that is lattice-matched or relaxed at growth temperature can acquire strain as film and substrate contract differently. Thick buffers, compound-semiconductor-on-silicon stacks, and bonded/heterogeneous platforms may bow, crack, or generate new dislocations. Measure strain and curvature after the complete thermal cycle. **Strain engineering is useful only when transferred to the active region.** Embedded SiGe may carry compressive stress, Si:C or highly doped Si:P can create tensile components, and Si/SiGe superlattices support nanosheet architectures. Geometry, relaxation, facets, contact formation, pattern density, and later anneals determine how much strain reaches the channel. Blanket film strain is not device strain. **Composition grading trades abruptness for defect management.** A graded SiGe buffer distributes mismatch over thickness and can promote controlled relaxation, but creates crosshatch, threading dislocations, long growth time, and dopant/impurity integration issues. Step grading, reverse grading, chemical-mechanical polishing, and defect filters change the trade. The final virtual substrate must be judged by both relaxation and usable surface quality. **Polarity and anti-phase boundaries matter in polar-on-nonpolar growth.** III–V materials on silicon can nucleate in opposite sublattice phases when the seed surface presents equivalent terraces, producing anti-phase boundaries. Substrate miscut, step preparation, nucleation layers, selective-area geometry, and growth sequence can suppress or confine them. Lattice matching alone cannot solve polarity. **Threading dislocations are not the only extended defects.** Stacking faults, twins, basal-plane dislocations, partials, inversion domains, V-pits, micropipes, and cracks occur depending on material and growth mode. Each has a different device consequence. Defect inspection must distinguish type, orientation, density, size, and spatial clustering rather than report a single count. **Autodoping originates outside the commanded dopant flow.** Dopant can evaporate or diffuse from the substrate, buried layers, backside, susceptor, chamber walls, or previously processed wafers and incorporate into the growing layer. Gas-phase transport and solid-state outdiffusion produce different profiles. Back-seal layers, reduced temperature, reactor design, sequence, and chamber dedication are possible controls. **In-situ doping changes surface kinetics.** Boron, phosphorus, arsenic, carbon, nitrogen, magnesium, silicon, and other dopants can alter rate, morphology, segregation, strain, defect formation, and precursor decomposition. Active concentration is not equal to total incorporated concentration. Row 2249 should own the detailed gas-to-active-dopant problem; the epitaxy page establishes why it cannot be separated from crystal growth. **Dopant transitions have memory and segregation tails.** Valve response, line volume, wall adsorption, gas residence, surface reservoir, and solid segregation broaden an intended abrupt change. Growth interrupts may sharpen one interface while increasing contamination or roughening. SIMS needs depth-resolution correction and should be paired with electrical profiling or device response. **Selective epitaxy balances deposition and removal.** On crystalline openings, registry enables epi incorporation; on oxide or nitride, unwanted nuclei may be etched or prevented during their incubation. Halogen chemistry, silicon partial pressure, temperature, pattern loading, defect sites, and mask condition set selectivity. Row 2248 should own the full selectivity/facet/loading window rather than letting this platform page absorb it. **Selectivity loss is usually localized first.** Particles, mask pinholes, polymer, plasma damage, moisture, scratches, or residues become nucleation sites on dielectric. Sparse mushrooms can be catastrophic even when blanket selectivity appears excellent. High-area patterned inspection and defect classification are necessary; a witness oxide coupon is insufficient. **Pattern loading changes local supersaturation.** A wafer with little exposed silicon distributes precursor differently from a wafer with large openings. Diffusion over masks, consumption at openings, etchant balance, boundary-layer depletion, pitch, recess depth, and wafer position change growth rate and composition. Pattern-density splits must cover the product design space. **Facets are crystallographic process outputs.** Different planes grow and etch at different rates, so recessed source/drain volumes develop geometry that depends on chemistry, temperature, strain, mask orientation, and time. Facets affect strain, junction placement, silicide/contact area, gap to the gate, and void formation. Measure three-dimensional shape, not only center thickness. **Recess quality limits regrowth quality.** Plasma etch leaves damage, residue, sidewall polymer, microtrenching, and crystal-plane roughness. Wet or vapor clean can remove damage but also change dimensions. Pre-bake may smooth or enlarge the recess. Cross-sectional defect review should connect the etch-clean sequence to stacking faults and interface defects in epi. **Wafer temperature is difficult and decisive.** Pyrometer emissivity changes with film, pattern, backside condition, coating, and viewport; thermocouples measure hardware rather than the wafer; lamps and susceptor produce radial/azimuthal modes. Calibrate against rate, desorption transitions, melt-point standards where appropriate, or other physical references. Report actual thermal evidence with the recipe. **Susceptor and chamber coatings change growth.** They alter emissivity, heat transfer, precursor consumption, surface recombination, memory, and particles. A coated susceptor may change real wafer temperature at unchanged lamp power. Fresh-clean, seasoned, and end-of-campaign response must be included in qualification. **Haze is a symptom, not a mechanism.** Surface roughness, pits, particles, hillocks, slip, stacking faults, or non-epi deposits can scatter light. Automated haze maps are valuable for excursions, but microscopy and composition identify the cause. A low average haze can coexist with a small population of lethal defects. **Slip is a thermal-mechanical failure.** Wafer temperature gradients, rapid ramps, backside particles, edge support, heavy films, and crystal strength generate resolved shear stress that moves dislocations. Slip lines may appear after an apparently clean epi process and can propagate into devices. Temperature uniformity, ramp design, backside cleanliness, support geometry, and wafer history are coupled controls. **Thickness metrology must match the structure.** Reflectometry and ellipsometry work well when optical contrast and models are constrained; FTIR interference can measure thick epitaxial layers; cross-sectional microscopy provides local truth; gravimetry or destructive methods may support special cases. Composition grading, doping, roughness, and multilayers complicate optical fits. **High-resolution X-ray diffraction measures reciprocal-space structure.** Symmetric and asymmetric scans, rocking curves, reciprocal-space maps, and reflectivity can constrain composition, strain, relaxation, thickness, tilt, and mosaicity. Results depend on elastic constants, model structure, grading, and instrument resolution. Composition and strain are coupled, so one peak position does not determine both independently. **Raman spectroscopy provides local strain and composition sensitivity with caveats.** Peak positions and shapes respond to strain, alloy composition, temperature, doping, confinement, and laser heating. Calibration depends on orientation and geometry. Raman maps are excellent for patterned strain when anchored by composition and temperature controls. **TEM reveals interfaces and defects but samples a tiny volume.** Cross-sectional high-resolution TEM, STEM imaging, diffraction, and chemical maps show registry, dislocations, stacking faults, facets, and intermixing. Sample preparation can introduce damage and selection bias. Use TEM to identify mechanisms, then connect them to wafer-scale monitors. **AFM and surface diffraction see different aspects of morphology.** AFM measures selected spatial bandwidth and reveals terraces, step bunches, pits, and crosshatch; LEED/RHEED or surface X-ray methods probe order/reconstruction. Scan size, tip, filtering, and site selection matter. Combine local morphology with full-wafer haze and defect inspection. **Composition metrology must distinguish total, substitutional, and active fractions.** SIMS reports elemental depth with matrix and resolution limits; XRD infers composition only through a strain/material model; atom probe or TEM methods are local; Hall and spreading-resistance methods report electrically active response under assumptions. Carbon or dopant incorporated interstitially does not deliver intended strain or carriers. **Defect density needs area and detection-limit accounting.** Etch-pit density, X-ray topography, optical inspection, cathodoluminescence, photoluminescence, TEM, and electrical mapping see different defects and sample areas. Zero observed defects means an upper confidence bound, not zero true density. Critical applications need large-area sampling and tail statistics. **Interface abruptness should be measured after the full thermal budget.** A sharp as-grown chemical profile may broaden during later anneal, while segregation during growth creates an asymmetric tail before any anneal. SIMS convolution, sputter mixing, roughness, and crater shape limit apparent width. Correlate chemical, strain, and electrical interfaces. **Electrical qualification closes the loop.** Sheet resistance, Hall mobility and carrier density, spreading resistance, junction leakage, contact resistivity, lifetime, breakdown, and device parameters consume the grown crystal differently. A film can look excellent by XRD yet fail through contamination or point defects. The intended device structure is the final epi monitor. **A qualification matrix should perturb physical mechanisms.** Sweep seed clean and queue time; temperature across desorption, step flow and relaxation; precursor partial pressure across rate and gas-phase reaction; carrier and pressure across transport; composition and thickness across critical strain; loading and pattern density across local supply; dopant transitions across memory; and chamber age across thermal and wall-state drift. **Factor interactions define the usable window.** The clean needed at one temperature may roughen at another; the halogen dose that preserves selectivity may suppress growth at low precursor pressure; a Ge fraction that is coherent at one thickness may relax after a thermal cycle; dopant incorporation changes with rate. Designed experiments and mechanistic maps are more transferable than single-factor recipes. **Tool matching compares response surfaces.** Match actual wafer temperature, rate, thickness and composition maps, strain/relaxation, morphology, defects, dopant profiles, particles, and device monitors across load, recipe perturbation, and chamber age. Identical gas flows and lamp powers do not create identical epitaxy when geometry, emissivity, conductance, and wall state differ. Production control should combine leading and lagging indicators. Leading inputs include precursor source condition, pressure/flow, carrier purity, temperature zones, rotation, clean/queue time, chamber and susceptor exposure, exhaust conductance, and maintenance. Lagging outputs include growth rate, map modes, composition/strain, defects/haze, Rs, interface or lifetime monitors, and periodic microscopy/SIMS. Safety follows the precursor and temperature set. Silane, disilane, germane, phosphine, arsine, diborane, hydrogen, ammonia, metal-organics, HCl, chlorine, and other sources can be pyrophoric, toxic, corrosive, or flammable. Hot surfaces, UHV sources, abatement, and reactive deposits add hazards. Gas cabinets, compatible delivery, detection, purge, ventilation, interlocks, maintenance controls, and current SDS/site procedures are mandatory. Exhaust and abatement are process hardware. Chloride deposits, silicon/germanium powder, dopant residue, metal-organic decomposition products, and pump coatings change conductance and create maintenance exposure. Track foreline pressure, throttle response, pump and abatement state, deposited mass, and clean endpoint. Safe cleanout must address the actual residue chemistry. **The honest epitaxy specification names the seed, layer, strain, and evidence.** State substrate orientation/miscut and surface preparation; material and composition profile; thickness; coherent, relaxed, or graded strain state; dopant profile; morphology; defect classes and sampling; interface requirements; and downstream thermal history. “Epi” alone does not define a crystal suitable for manufacture. **Production-worthy epitaxy is a controlled continuation of a known seed surface.** It reaches the required thickness, composition, doping, registry, strain, morphology, interface abruptness, and defect tail across the actual wafer and pattern set. It remains stable through later thermal, etch, contact, release, and package steps, and its chamber lifecycle is controlled before drift reaches product. --- ## Epitaxy control and qualification workflow ```flowchart {"rows":[{"type":"nodes","items":[{"title":"Seed surface","sub":"orientation · clean · steps","tone":"blue"},{"title":"Arrival flux","sub":"chemistry · beams · transport","tone":"purple"},{"title":"Surface kinetics","sub":"adsorb · diffuse · incorporate","tone":"amber"}]},{"type":"arrow"},{"type":"nodes","items":[{"title":"Crystal state","sub":"registry · alloy · doping","tone":"blue"},{"title":"Strain state","sub":"coherent · graded · relaxed","tone":"purple"},{"title":"Defect state","sub":"misfit · threading · planar","tone":"red"}]},{"type":"arrow"},{"type":"nodes","items":[{"title":"Integration","sub":"pattern · thermal · contacts","tone":"amber"},{"title":"Correlated evidence","sub":"XRD · TEM · AFM · SIMS","tone":"green"},{"title":"Device release","sub":"electrical · optical · yield","tone":"green"}]}]} ``` ### Seed-surface release gate

### Coherency and critical thickness

### Wafer and pattern response

Following the seed surface through oxide removal, adsorption, terrace diffusion, step incorporation, alloy and dopant addition, coherent strain, relaxation, defect propagation, patterned loading, and device response is the kind of surface-to-system connection Chip Foundry Services makes explicit—so epitaxy is qualified as controlled crystal continuation rather than treated as a special name for CVD.