CMP erosion is the undesirable thinning and loss of dielectric insulating oxide between closely spaced metal interconnect lines in high-density pattern arrays during chemical mechanical planarization, measured as the vertical step height difference between the unpatterned field oxide and the recessed oxide within the dense array ($h_{\text{erosion}} = z_{\text{field}} - z_{\text{array}}$). While dishing refers to the concave recess of individual metal lines below their surrounding oxide walls, erosion represents the localized loss of the oxide walls themselves due to concentrated mechanical pressure and prolonged over-polishing across dense feature layouts. Left unmitigated, dielectric erosion thins the inter-layer dielectric (ILD) stack, creates wafer-scale height topography steps that cause scanner defocus in subsequent lithography steps, and increases inter-wire capacitive coupling.

Effective contact pressure concentration on remaining dielectric oxide pillars drives array erosion. In chemical mechanical polishing, when bulk metal clears from a wafer, the softer copper lines recess slightly, shifting the entirety of the carrier downward force ($P_{\text{down}}$) onto the exposed dielectric oxide walls. In a dense array with metal area fraction $\rho_{\text{metal}} = w / (w + s)$, the effective contact pressure supported by the remaining oxide is inversely proportional to the dielectric area:

In high-density arrays ($\rho_{\text{metal}} = 80\%$), effective local contact pressure on the narrow oxide pillars spikes by a factor of 5 ($P_{\text{eff}} = 5 P_{\text{down}}$). Under Preston's removal law ($RR = k_{\text{Preston}} P_{\text{eff}} V$), this concentrated pressure accelerates dielectric oxide removal, eroding the oxide downward at rates far higher than surrounding unpatterned field oxide.

Dielectric erosion compounds with line dishing to produce severe total metal loss in dense wiring buses. Total vertical recess of metal wires in an array is the cumulative sum of both array-level oxide erosion and feature-level metal dishing:

While dishing dominates in isolated wide lines ($w > 5\ \mu\text{m}$), erosion dominates in dense narrow line arrays (e.g., dense SRAM bitlines and standard cell local routing at $30\text{--}50\text{ nm}$ pitch). When severe erosion strips $30\text{--}40\text{ nm}$ of dielectric oxide, adjacent metal wires risk punching through to underlying interconnect layers, causing destructive inter-metal dielectric breakdown.

High-selectivity chemical slurries with self-stopping planarization behavior suppress oxide erosion. To prevent runaway dielectric removal during necessary over-polish cycles, foundries utilize high-selectivity chemical mechanical polishing slurries. In Shallow Trench Isolation (STI) and copper barrier CMP, ceria-based ($\text{CeO}_2$) or tailored colloidal silica slurries with amino acid or polymer additives achieve oxide-to-nitride or copper-to-dielectric removal selectivity exceeding $50:1$. Once the pad touches the underlying planar dielectric, chemical passivation halts further removal, creating an automatic "self-stopping" planarization endpoint.

Layout pattern density design rules enforce strict window constraints to prevent localized erosion hotspots. Modern foundry Design Rule Manuals (DRM) mandate strict local and global metal density limits across multiple sliding inspection windows (e.g., $20\ \mu\text{m} \times 20\ \mu\text{m}$ to $100\ \mu\text{m} \times 100\ \mu\text{m}$ windows):

Automated Dummy Metal Fill algorithms insert floating dielectric slotting into high-density metal planes and add dummy metal patches into sparse oxide zones, maintaining a flat uniform density landscape across the entire die to eliminate pressure concentration gradients.

Integrated eddy-current and optical reflectance endpoint systems minimize over-polish duration. Because oxide erosion accumulates linearly with over-polish time ($h_{\text{erosion}} \propto t_{\text{overpolish}}$), precision endpoint detection is critical. In-situ eddy-current sensors embedded in the rotating platen measure remaining bulk copper thickness with sub-5nm resolution, automatically triggering low down-force transitions ($P < 1.0\text{ psi}$) before barrier breakthrough. Real-time multi-wavelength spectrometer optics monitor the color shift of underlying dielectric oxide, terminating the polish cycle within 2 seconds of complete barrier clearing.

st=>start: Wafer enters Platen 2 with patterned dense metal arrays and barrier layer
density=>operation: Verify EDA layout pattern density compliance (20% ≤ ρ_metal ≤ 60%)
soft_land=>operation: Polish barrier at low down-force (P ≤ 1.2 psi) to reduce effective pressure P_eff
eddy=>operation: Track real-time platen eddy-current and optical reflection spectrum signals
endpoint=>condition: Optical endpoint detected across dense array and field oxide boundaries?
overpolish=>operation: Execute minimal timed over-polish (5–10s) with high-selectivity ceria/silica slurry
inspect=>condition: Total oxide erosion h_erosion ≤ 5.0nm across all dense arrays?
pass=>end: Qualified planar dielectric surface ready for subsequent ILD deposition
st->density->soft_land->eddy->endpoint
endpoint(yes)->overpolish->inspect
endpoint(no)->eddy
inspect(yes)->pass
inspect(no)->soft_land

Achieving nanometer-scale multi-layer interconnect yield requires treating CMP erosion as an effective-pressure-local-pattern-density-and-overpolish lens. By harmonizing CAD layout density rules, multi-zone carrier force balancing, self-stopping slurry chemistry, and microsecond-level in-situ endpoint detection, semiconductor foundries prevent dielectric thinning across dense functional blocks. Rigorous erosion management guarantees that billion-transistor ICs maintain precise interlayer dielectric thickness, robust dielectric breakdown margins, and flat planar topography across all wiring tiers.