ESD Protection Overview

On-chip ESD protection structures are designed into every I/O pad and power pin of an integrated circuit to shunt electrostatic discharge current safely to ground without damaging internal circuitry.

Protection Strategy

• Primary Clamp: Large ESD device at each I/O pad—handles full ESD current. Must turn on fast (< 1ns for CDM) and carry high current (> 1A for HBM).
• Secondary Clamp: Smaller device closer to the protected circuit—limits residual voltage if primary clamp is insufficient.
• Power Clamp: ESD device between VDD and VSS rails—provides discharge path for power pin ESD events.
• Rail Clamp: Triggers during ESD event to short VDD to VSS, providing low-impedance current path.

ESD Device Types

• Grounded-Gate NMOS (ggNMOS): NMOS with gate tied to ground. Triggers via drain-body junction avalanche. Simple, widely used.
• Diode Strings: Forward-biased diode chain to VDD or VSS. Fast turn-on, scalable, predictable. Most common at advanced nodes.
• SCR (Silicon Controlled Rectifier): Lowest area per ESD current capability. Very high current handling in small footprint. Used where area is critical.
• RC-Triggered Clamp: RC network detects fast ESD transient and turns on a large NMOS clamp. Used for power rail protection.

Design Challenges

• Shrinking Design Window: ESD structures must trigger above normal operating voltage but below oxide breakdown voltage. At advanced nodes, this window narrows.
• Leakage: ESD devices must not increase standby leakage during normal operation.
• Area Cost: ESD structures consume pad area. Designers minimize ESD device size while meeting protection targets.
• CDM Protection: Sub-nanosecond events require extremely fast turn-on—most challenging ESD spec to meet.