ESD Design (On-Chip) — designing the protection circuits and I/O pad structures that safely shunt electrostatic discharge events away from sensitive core transistors.

Protection Strategy

• Every I/O pad has ESD protection between:
• Pad to VDD (diode clamp)
• Pad to VSS (GGNMOS or diode)
• VDD to VSS (power clamp — RC-triggered big NMOS)
• Forms a "protection ring" around the entire chip

ESD Design Rules

• Metal bus width: ESD current is massive (~1A) — power buses near pads must be wide enough
• Guard rings: Surround ESD devices to collect substrate current and prevent latch-up
• Ballasting: Ensure uniform current distribution across multi-finger ESD devices
• No series resistance: Signal path from pad to ESD device must have minimal R

Layout Considerations

• ESD devices placed as close to pad as possible
• Dedicated ESD power bus routing (not shared with core logic)
• Back-to-back diodes for cross-domain protection

Full-Chip ESD Verification

• EDA tools verify complete discharge paths exist for every pin
• Check current density in all wires during ESD event
• Simulate ESD event through SPICE to verify clamping voltage and survival

ESD Testing

• Fabricated chips tested to HBM 2kV and CDM 500V standards
• Failure analysis if protection is insufficient → re-spin with beefier protection

ESD design is mandatory for every chip — it's unglamorous but essential, because a chip that can't survive handling is worthless.