ESD protection is the on-chip circuit and device network that safely shunts electrostatic discharge (ESD) current — thousands of volts and several amperes lasting nanoseconds — away from the fragile core transistors before the voltage can rupture gate oxides, melt junctions, or fuse metal lines. Every I/O pad on every chip has ESD clamps; without them a single human touch (human-body model: 2–4 kV, 1.5 A peak, ~150 ns pulse) would instantly destroy the gate oxide of a modern transistor (breakdown at 3–5 V across a 1–2 nm oxide). ESD design is an invisible but mandatory tax on every chip — consuming pad area, adding capacitance, and requiring careful co-design with the I/O circuits it protects.

ESD event models — what the chip must survive. Industry standards define three stress waveforms that every product must pass:

CDM is the most dangerous in manufacturing: a small charged package dumps all its stored energy through a single pin in <5 ns — creating very high di/dt and localized heating that can blow out the thinnest dielectric or melt a contact. Modern spec: HBM ≥ 2 kV, CDM ≥ 250 V.

The ESD protection network — clamps at every pin. A complete ESD protection strategy places discharge devices at three levels:

1. Primary clamp (at the pad). A large-area device (diode, SCR, or grounded-gate NMOS — ggNMOS) directly between the pad and VDD/VSS rails. It turns on at a trigger voltage below oxide breakdown and carries the bulk of the ESD current. Must handle 1+ A without damage. 2. Secondary clamp (between rail and core). A smaller device between the pad and the core input gate — limits the residual voltage that reaches the protected circuit after the primary fires. Typically a series resistor + small diode pair. 3. Power clamp (VDD-to-VSS). A large RC-triggered clamp across the supply rails. During an ESD event (which charges VDD relative to VSS), this clamp turns on and provides a low-impedance path from VDD to VSS. Without it, current returning from a pad-to-VDD event has no path to VSS and the voltage across the core rises dangerously.

ESD design window — the voltage budget. The clamp must trigger and conduct at a voltage above normal operating range but below the damage threshold of the protected circuit:

$$V_{\text{operating}} < V_{\text{trigger}} < V_{\text{clamp}} < V_{\text{oxide\,breakdown}}$$

At a 5 nm node with 0.75 V supply and ~4 V oxide breakdown: the trigger voltage must be 1.5–3 V, and the clamping voltage (voltage across the device during conduction) must stay below ~3.5 V even at peak ESD current. This window is tight — and getting tighter every node as oxide thickness and breakdown voltage both decrease.

Clamp device options:

The capacitance penalty — ESD vs high-speed I/O. Large ESD diodes add parasitic capacitance to the pad node — 0.2–1 pF per clamp. At multi-GHz signaling rates (PCIe Gen5 at 32 GT/s, DDR5, SerDes), this capacitance degrades signal integrity and limits bandwidth. The trade-off: smaller clamps for high-speed pads (reduced ESD robustness, often 500 V HBM instead of 2 kV) or novel clamp topologies (T-diode, dual-diode with isolation, or distributed ESD with series inductors) that minimize capacitance while maintaining protection.

CDM protection — the hardest problem. CDM events are so fast (<5 ns) that the pad-level primary clamp may not fully turn on before the voltage spike reaches the core. CDM protection requires: (1) very low resistance in the discharge path (wide metal connections from pad to clamp to rail); (2) fast-triggering devices (forward-biased diodes, not snapback NMOS); (3) distributed rail resistance low enough that the clamp voltage doesn't drop across the power grid before reaching the core. At 3 nm, CDM simulation requires full-chip RC extraction of the power grid — a >24-hour computation — to verify that no internal node exceeds its breakdown voltage during a CDM event at any pin.

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ESD in advanced nodes — the shrinking window. At each new node, gate oxide gets thinner and breakdown voltage drops. Meanwhile, supply voltage reduction slows (stuck at 0.7–0.8 V for performance). The ESD design window between operating voltage and oxide breakdown shrinks from ~4 V at 28 nm to <2 V at 3 nm. This forces the use of lower-trigger-voltage clamps (stacked diodes, precision-tuned SCRs) and tighter simulation accuracy — a 0.3 V error in trigger prediction can mean the difference between a passing and failing CDM qualification.

What ESD means for AI chip design. A large GPU die has 5000–10000 I/O and power pads, each requiring ESD protection. The cumulative pad-ring ESD capacitance contributes to the total I/O power budget, and ESD-related area overhead in the pad ring reduces the silicon available for compute. High-speed interfaces (HBM PHY at 8+ Gbps, PCIe Gen6 at 64 GT/s, NVLink at 112 Gbps) are especially sensitive — each incremental femtofarad of ESD capacitance costs signal margin. The ESD team and the high-speed I/O team negotiate the protection level for every pad: full 2 kV HBM for low-speed pads, reduced 500 V or 200 V for the highest-speed SerDes — a risk the product reliability team must sign off on.