Chemical etching. uses reaction chemistry chosen to remove a target material faster than adjacent masks, stop layers, channels, spacers, liners, or substrates. Selectivity is the target etch rate divided by the protected-material rate under the same feature and process conditions. A high blanket ratio is useful but insufficient: a manufacturing process must preserve critical dimensions and surfaces through the full endpoint and overetch window, across dense and isolated patterns, aspect ratio, wafer position, loading, temperature, chemistry age, and upstream material variation. A semiconductor unit process is never specified by one nominal recipe. Its production definition includes incoming surface state, materials and pattern geometry, chamber or bath configuration, chemical purity, temperature, pressure, flow, power, time, endpoint or dose, wafer handling, queue time, allowable excursions, and the metrology reference used to accept the result. The same nominal film or removal can behave differently after a change in substrate, feature pitch, pattern density, chamber history, carrier, or upstream clean. Process integration therefore treats every step as both a material transformation and a source of downstream variability.
Physical and chemical mechanisms. Selectivity can arise from favorable target reaction, formation of a volatile or soluble product, passivation of the stop material, crystal orientation, electrochemical potential, ligand binding, or controlled oxidation-reduction. Transport determines whether reactant reaches buried sacrificial material and products escape. By-products can inhibit or catalyze local etch. A protected surface may suffer roughening or incubation even when average loss is small. For nanosheet release, long lateral access paths and extremely thin channels magnify gradients, stiction, capillary forces, and small selectivity errors. Mechanism and transport must be separated. Reactants are delivered through gas flow, liquid convection, diffusion, adsorption, ion motion, or charged-species transport; products must desorb, dissolve, or escape without redeposition. Surface reaction probability changes with coverage, crystal orientation, activation energy, charging, local electric field, and by-product concentration. At patterned dimensions, loading, aspect-ratio-dependent transport, microloading, capillary forces, surface tension, and feature-scale heat transfer create behavior that blanket-wafer rate cannot predict. Selectivity is a ratio under declared conditions, not a timeless material constant.
Equipment, recipe, and manufacturing control. The process can be liquid, vapor, remote plasma, downstream radical, thermal, or cyclic. Chemistry, dilution, pressure, flow, temperature, wafer spacing, agitation, plasma dissociation if used, exposure, purge, endpoint, and rinse/dry are co-optimized. The claimed material pair must name composition: SiGe selectivity changes with germanium fraction, strain, doping, oxidation, and surface state; silicon nitride and oxide behavior changes with deposition method and stoichiometry. Ratios above 100:1 may be integration targets for some advanced releases, but must be demonstrated on the actual stack rather than generalized. Manufacturing control begins with qualified incoming material, chamber matching, chemical and gas specifications, calibrated delivery, wafer temperature evidence, and preventive-maintenance state. Recipes define ramp and stabilization phases as well as the main exposure. Dummy wafers, seasoning, pre-coats, endpoint windows, rinse and dry sequences, and post-process queue limits can be essential. Contamination control distinguishes particles, mobile ions, transition metals, organics, moisture, native oxide, residues, and cross-contamination between incompatible materials. Automated fault detection watches traces, but a statistically normal sensor does not prove a normal wafer.
Applications, alternatives, and integration trade-offs. Gate-all-around fabrication selectively removes SiGe sacrificial layers to release silicon nanosheets or selectively removes silicon to release SiGe channels in alternate flows. MEMS releases sacrificial oxide or other films around mechanical structures. Contact and via cleans remove native oxide while preserving semiconductor and dielectric. Metal etches remove one conductor without corroding barriers or adjacent metals. Oxide-versus-nitride and nitride-versus-oxide selectivity support spacers, self-aligned patterning, and stop layers. Isotropic access can be valuable where directional RIE cannot reach under a structure. Integration choices balance profile, conformality, selectivity, damage, thermal budget, material compatibility, throughput, defectivity, uniformity, equipment availability, consumables, waste, and cost of ownership. A process that gives excellent blanket-film data may fail in dense and isolated structures or at wafer edge. Advanced logic, memory, image sensors, MEMS, photonics, power devices, RF, packaging, and compound semiconductors place different priorities on sidewall shape, interface quality, stoichiometry, stress, hydrogen, charging, corrosion, and particle tolerance. Technology transfer must preserve mechanism, not just copy setpoints.
| Selective-etch pair | Example chemistry family | Protected mechanism | Integration use | Key risk |
|---|---|---|---|---|
| SiGe relative to Si | Oxidation / halogen / wet or vapor selective families | Preferential SiGe reaction or Si passivation | GAA silicon nanosheet release | Channel loss, Ge dependence, lateral loading |
| Si relative to SiGe | Halogen or alkaline selective families | Composition-dependent surface chemistry | Alternative GAA release | SiGe roughness and oxidation |
| SiO₂ relative to Si₃N₄ | HF-based wet or vapor chemistry | Nitride reacts much more slowly | Sacrificial oxide and stop-layer use | Stiction, watermarks, nitride loss over time |
| Metal relative to dielectric / barrier | Redox, complexing, plasma or wet chemistry | Dielectric inertness or barrier passivation | Metal patterning and residue clean | Galvanic corrosion and residues |
<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,BlinkMacSystemFont,Segoe UI,Roboto,sans-serif">
<rect x="0" y="0" width="760" height="470" fill="#0d1117"/>
<text x="380" y="28" fill="#e6edf3" font-size="21" font-weight="700" text-anchor="middle">Chemical Etching Technical Microarchitecture</text>
<text x="380" y="48" fill="#8b98a5" font-size="12" text-anchor="middle">Detailed Domain Pipeline, Architectural Blocks & Engineering Performance Optimization (ID 10660)</text>
<!-- FAB CROSS SECTION (2 Main Panels) -->
<g transform="translate(25, 75)">
<rect width="345" height="325" fill="#161b22" stroke="#30363d" stroke-width="1.5" rx="8"/>
<text x="172.5" y="25" fill="#f59e0b" font-size="13" font-weight="700" text-anchor="middle">1. Physical Layer Cross-Section</text>
<rect x="20" y="240" width="305" height="60" fill="#0d1117" stroke="#30363d" rx="4"/>
<text x="172.5" y="275" fill="#8b98a5" font-size="11" font-weight="600" text-anchor="middle">Silicon Substrate / Base Crystal Wafers</text>
<rect x="20" y="170" width="305" height="60" fill="#1f2937" stroke="#b45309" rx="4"/>
<text x="172.5" y="205" fill="#fbbf24" font-size="11" font-weight="600" text-anchor="middle">Dielectric Oxide & Isolation Barriers</text>
<rect x="20" y="100" width="305" height="60" fill="#0f172a" stroke="#f59e0b" stroke-width="1.5" rx="4"/>
<text x="172.5" y="135" fill="#e6edf3" font-size="12" font-weight="700" text-anchor="middle">Active Junctions & Nanometer Channel</text>
<rect x="40" y="45" width="70" height="45" fill="#d97706" rx="3"/>
<text x="75" y="72" fill="#ffffff" font-size="10" font-weight="700" text-anchor="middle">Source</text>
<rect x="137.5" y="45" width="70" height="45" fill="#fbbf24" rx="3"/>
<text x="172.5" y="72" fill="#0d1117" font-size="10" font-weight="700" text-anchor="middle">Gate</text>
<rect x="235" y="45" width="70" height="45" fill="#d97706" rx="3"/>
<text x="270" y="72" fill="#ffffff" font-size="10" font-weight="700" text-anchor="middle">Drain</text>
</g>
<g transform="translate(390, 75)">
<rect width="345" height="325" fill="#161b22" stroke="#30363d" stroke-width="1.5" rx="8"/>
<text x="172.5" y="25" fill="#f59e0b" font-size="13" font-weight="700" text-anchor="middle">2. Process & Materials Specs</text>
<rect x="15" y="45" width="315" height="75" fill="#0d1117" stroke="#30363d" rx="5"/>
<text x="30" y="70" fill="#fbbf24" font-size="11" font-weight="700">Deposition & Etch Selectivity:</text>
<text x="30" y="95" fill="#8b98a5" font-size="10">> 50:1 Target Selectivity, Sub-nm Uniformity Control</text>
<rect x="15" y="135" width="315" height="75" fill="#0d1117" stroke="#30363d" rx="5"/>
<text x="30" y="160" fill="#fbbf24" font-size="11" font-weight="700">Thermal & Stress Budget:</text>
<text x="30" y="185" fill="#8b98a5" font-size="10">Rapid Thermal Anneal (RTA) < 1050°C, Stress Migration Low</text>
<rect x="15" y="225" width="315" height="80" fill="#0d1117" stroke="#b45309" rx="5"/>
<text x="30" y="250" fill="#3fb950" font-size="11" font-weight="700">Yield & Defect Metric:</text>
<text x="30" y="275" fill="#e6edf3" font-size="10">Critical Dimension (CD) Variation < 1.2%, D0 Defect < 0.05/cm²</text>
</g>
<!-- Key insight bar -->
<rect x="25" y="415" width="710" height="22" rx="3" fill="#0b1220" stroke="#233043" stroke-width="0.8"/>
<text x="380" y="430" fill="#fbbf24" font-size="9" font-weight="700" text-anchor="middle">Key Insight: Optimal Chemical Etching architecture balances performance throughput, systemic latency, and physical constraints.</text>
<text x="380" y="460" fill="#6b7684" font-size="11" text-anchor="middle">Technical specification & verification reference for Chemical Etching (Row ID 10660)</text>
</svg>
Metrology, qualification, and CFS connection. Qualification reports target loss, stop-layer loss, ratio, profile, lateral reach, roughness, residue, composition, electrical surface quality, mechanical survival, and uniformity versus overetch. Cross-sectional TEM or SEM resolves released gaps and channel loss; ellipsometry and blanket films provide rate baselines; XPS or SIMS tracks residues and surface change; electrical structures reveal mobility, interface traps, contact resistance, leakage, and breakdown. Pattern-density and aspect-ratio arrays expose loading. Collapse, adhesion, watermark, corrosion, and post-etch queue stability are included. Verification uses complementary measurements. Film thickness, refractive index, stress, composition, density, roughness, sheet resistance, critical dimension, profile, recess, residue, and defect maps are correlated with equipment traces. Cross-sectional SEM or TEM resolves shape; AFM and optical methods measure surface and thickness; XPS, SIMS, FTIR, ellipsometry, XRF, four-point probe, and electrical structures reveal chemistry and function. Split lots vary the mechanism-driving parameters, while patterned monitor vehicles expose loading. Run-to-run control uses stable references, gauge studies, control limits, excursion ownership, and retained raw data. Acceptance criteria separate target, guardband, control, screening, and qualification limits. Material or supplier changes reopen assumptions about purity, surface state, stress, transport, equipment compatibility, defectivity, reliability, and downstream electrical behavior. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.
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