Semiconductor Etch Processes are the subtractive patterning techniques that selectively remove material from the wafer according to photoresist or hard mask patterns — ranging from isotropic wet etching to highly anisotropic plasma (dry) etching that achieves vertical sidewalls with nanometer precision, essential for defining transistor gates, interconnect trenches, and contact holes at every technology node.

Dry Etch (Plasma Etch):

• Reactive Ion Etch (RIE): chemically reactive plasma species (radicals, ions) combined with directional ion bombardment — chemical component provides selectivity (different materials etch at different rates in the same chemistry); physical component (ion energy) provides anisotropy (vertical sidewalls)
• ICP (Inductively Coupled Plasma): separate RF sources for plasma generation (ICP coil) and ion energy (substrate bias) — independent control of ion density and ion energy enables high etch rate with controlled damage; standard for advanced BEOL and FEOL patterning
• CCP (Capacitively Coupled Plasma): single or dual RF-powered parallel plates — simpler design with coupled ion density and energy control; used for less demanding etch steps; dual-frequency CCP provides some independent control
• Etch Chemistry: CF₄/CHF₃/C₄F₈ for oxide/nitride etch, Cl₂/HBr for silicon/poly etch, BCl₃/Cl₂ for metal etch — gas mixtures tuned for selectivity (etch rate ratio between target material and mask/underlayer), etch rate, profile, and surface quality

Etch Control Parameters:

• Anisotropy: A = 1 - (lateral etch rate / vertical etch rate) — A=1 is perfectly anisotropic (vertical sidewalls); achieved through polymer passivation of sidewalls (C₄F₈ cycles in Bosch process) or ion-enhanced etch directionality
• Selectivity: ratio of target material etch rate to underlying or mask material etch rate — oxide-to-nitride selectivity of >20:1 achieved with C₄F₈/CO chemistry; low selectivity risks punch-through of thin underlying layers
• Critical Dimension Control: etch bias (CD change from lithographic pattern to etched feature) must be uniform ±1 nm across 300mm wafer — etch loading (pattern-density-dependent etch rate) and micro-loading (local pattern effects) controlled through chemistry optimization
• Etch Stop: detecting when etch reaches a specific layer — optical emission spectroscopy (OES) monitors plasma emission wavelengths characteristic of the layer being etched; endpoint detection triggers chemistry change or process stop

Atomic Layer Etching (ALE):

• Self-Limiting Process: surface modification step (chemical adsorption) followed by removal step (low-energy ion bombardment) — each cycle removes exactly one atomic layer (~0.5-1 Å) regardless of time; provides ultimate depth control
• Thermal ALE: sequential self-limiting chemical half-reactions (analogous to ALD) — fluorination followed by ligand exchange for oxide ALE; enables isotropic atomic-layer-precision etching for lateral recess applications
• Plasma ALE: surface modification by reactive gas adsorption, removal by low-energy Ar⁺ bombardment — directional (anisotropic) ALE for vertical profile control at atomic-layer precision; critical for FinFET fin recess and GAA nanosheet release
• Applications: gate etch with sub-nanometer depth control, spacer etch with atomic-level uniformity, 3D NAND channel hole etch — becoming essential at 3nm and below where conventional RIE lacks sufficient precision

Semiconductor etch processes are the pattern-definition workhorses of chip fabrication — every feature on a modern processor has been shaped by precisely controlled plasma chemistry, and the continued scaling of transistors to atomic dimensions drives the transition from conventional RIE to atomic layer etching for ultimate precision and control.