Plasma Etch Selectivity and Profile Control encompasses the precise tuning of plasma chemistry, bias power, pressure, and gas composition to achieve anisotropic removal of target films while minimizing attack on mask, underlayer, and adjacent materials — maintaining critical dimension (CD) control, sidewall angle, and surface smoothness across billions of features per wafer. Selectivity and profile engineering are the core challenges of dry etch process development at every technology node.
Selectivity is defined as the ratio of etch rates between the target material and a reference material (usually the mask or stop layer). For example, SiO2/Si selectivity of 50:1 means oxide etches 50× faster than silicon. High selectivity is achieved through selective passivation — etch byproducts or deliberately added gases form protective films on surfaces that should not be etched. In fluorocarbon-based oxide etch (using C4F8, C4F6, CHF3), a thin CFx polymer deposits on silicon and nitride surfaces (forming a protective layer) while being continuously sputtered from oxide surfaces by ion bombardment, enabling high oxide/Si and oxide/SiN selectivity.
Key etch chemistries and their selectivity mechanisms: SiO2 etch uses fluorocarbon gases (C4F8/C4F6 + Ar/O2) — fluorine attacks Si-O bonds while CFx polymer provides selectivity to Si and SiN. Silicon etch uses HBr/Cl2/O2 — the SiBrxOy passivation layer on sidewalls provides anisotropy while O2 addition forms SiO2 on nitride surfaces for selectivity. SiN etch uses CH2F2/CHF3/O2 — optimized for selectivity to oxide via careful C:F ratio in the fluorocarbon chemistry. Metal etch uses Cl2/BCl3 — aggressive chemistry for aluminum, with more specialized chemistries for advanced metals.
Profile control (achieving vertical sidewalls, controlled taper, or desired bowing) depends on the balance between: ion bombardment (directional, promotes anisotropy — controlled by bias voltage/power), chemical etching (isotropic, promotes lateral attack — controlled by radical flux and pressure), and passivation (deposits on sidewalls to block lateral etch — controlled by polymer-forming gas flows and substrate temperature). Higher bias = more anisotropic but potentially more damage. Higher pressure = more chemical but less directional. Colder wafer temperature strengthens sidewall passivation.
Advanced etch challenges include: etch depth loading (ARDE — narrower features etch slower due to restricted reactant transport); microloading (isolated features etch faster than dense arrays); notching at dielectric interfaces due to charge buildup; line edge/width roughness (LER/LWR) transferred or amplified from the resist pattern; and atomic layer etching (ALE) for sub-nanometer depth control in GAA inner spacer and channel release steps where conventional plasma etch cannot achieve the required precision.
Plasma etch selectivity and profile engineering represent the most nuanced process optimization in semiconductor manufacturing — balancing a half-dozen competing physical and chemical mechanisms simultaneously to carve features with atomic precision in three dimensions.