Home Knowledge Base Etch Selectivity in Semiconductor Processing

Etch Selectivity in Semiconductor Processing is the fundamental plasma and wet etch parameter that quantifies the removal rate ratio between the target material and the material that must be preserved — where achieving selectivities of 10:1 to >100:1 enables self-aligned processes, protects underlying layers during pattern transfer, and makes the multi-material stacks of advanced CMOS devices feasible to fabricate.

Why Selectivity Is Critical

Modern devices stack 10-20 different materials in close proximity. Etching one material (the target) requires minimizing removal of adjacent materials (stops or protectors). Without selectivity, every etch step would damage surrounding structures — a gate oxide etch would thin the spacer, a contact etch would erode the gate cap, and a via etch would punch through the etch stop liner.

Defining Selectivity

Selectivity = (Etch rate of target material) / (Etch rate of non-target material). A selectivity of 50:1 means 50 nm of target is removed for every 1 nm of non-target loss. Key fab selectivity requirements:

Etch StepTarget : StopRequired Selectivity
Contact etchSiO2 : SiN (gate cap)>20:1
Via etchSiO2 : SiCN (etch stop)>10:1
SiGe release (GAA)SiGe : Si (nanosheet)>100:1
Gate recessPoly-Si : SiO2 (gate oxide)>50:1
STI etchSi : SiO2 (hard mask)>10:1

How Selectivity Is Achieved

Etch Stop Layers

Deliberately-deposited thin films that provide etch selectivity where none would otherwise exist:

Etch Selectivity is the material discrimination capability that makes complex multi-layer fabrication possible — enabling each etch step to surgically remove exactly the intended material while leaving every surrounding structure untouched.

etch selectivity processselective etch chemistryetch stop layeretch ratio dielectricplasma etch selectivity

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