ethernet is the layered family of local- and wide-area networking standards that transports framed data over copper, fiber, and backplane channels from 10 megabits per second to 800 gigabits per second. It is now a critical AI-cluster fabric whose PHYs, switches, optics, congestion control, and RDMA behavior determine how effectively expensive accelerators scale.

Layered architecture and evolution. Ethernet defines frame transport at the data-link layer and a broad set of physical layers below it. A frame carries destination and source addresses, an EtherType or length, payload, and a frame check sequence; switches learn source locations and forward by destination MAC address. Full-duplex switched links replaced shared collision domains, while VLAN tags, link aggregation, quality of service, and jumbo frames support larger systems. Physical rates progressed from 10 Mb/s to 100 Mb/s, 1, 10, 25, 40, 50, 100, 200, 400, and 800 Gb/s by increasing symbol rate, lane count, and modulation efficiency. Each generation is a complete channel budget involving transmitter, package, connector, cable or fiber, receiver, clock recovery, and forward error correction.

PHY media, SerDes, and signaling. Copper twisted pair dominates access networks; direct-attach copper serves short rack links; optical modules and co-packaged optics address longer reach and high front-panel density. Early standards used binary signaling, while high-rate electrical and optical lanes increasingly use PAM4, encoding two bits in four amplitude levels at the cost of smaller eye openings and greater linearity demands. Serializer-deserializer lanes require feed-forward equalization, continuous-time linear equalization, decision-feedback equalization, clock-data recovery, lane deskew, and FEC. A 400G or 800G port is therefore a mixed-signal system, not merely a faster digital MAC. Power per bit, optical reach, connector loss, thermal density, and repairability influence the economically useful topology.

Ethernet for AI clusters. Distributed training sends gradients, activations, parameters, and checkpoint data between GPUs. RDMA over Converged Ethernet allows a NIC to place data directly into registered memory with little CPU involvement. RoCEv2 rides over UDP and IP, enabling routed fabrics, but loss and congestion must be controlled through mechanisms such as priority flow control, explicit congestion notification, data-center quantized congestion notification, careful queue design, and modern end-host algorithms. Rail-optimized topologies connect each accelerator interface to a corresponding leaf-spine plane. Collective libraries divide all-reduce traffic across paths and overlap it with computation. Tail latency, incast behavior, flow completion, packet reordering, and failure recovery matter alongside headline bandwidth.

Ethernet versus InfiniBand. InfiniBand traditionally offers a tightly integrated RDMA ecosystem, deterministic fabric features, mature collective offload, and strong congestion behavior. Ethernet offers a vast supplier base, familiar IP operations, routed scale, and convergence with storage and general data-center traffic. The comparison is implementation-specific: a well-engineered 400GbE or 800GbE RoCE fabric can support large training clusters, while a poorly tuned lossless configuration can suffer pause storms and head-of-line blocking. Teams should compare effective collective bandwidth, message-rate latency, topology oversubscription, switch buffering, telemetry, operational skill, component availability, and total power. Protocol labels alone do not predict job completion time.

Design and validation practice. MAC verification covers framing, pause behavior, VLANs, counters, and error injection. PCS and FEC verification covers lane alignment, gearbox operation, coding, correction limits, and fault signaling. PHY sign-off combines insertion and return loss, crosstalk, jitter, equalization adaptation, optical budgets, and bit-error measurements. Fabric tests create synchronized incast, all-to-all, all-reduce, link failures, routing changes, and mixed storage traffic while collecting queue occupancy and ECN marks. Network simulation should be correlated with switch and NIC counters. Capacity planning reserves margin for protocol overhead, imbalance, retransmission, and maintenance rather than treating line rate as application throughput. A production review should connect the architectural model to measurable requirements, sweep process, voltage, temperature, workload, and channel corners, and preserve assumptions beside every result. Teams should separate intrinsic block capability from system overhead, define pass and fail limits before simulation, and correlate behavioral models with transistor-level or cycle-accurate evidence. Useful sign-off artifacts include configuration, stimulus, seeds, tool versions, raw measurements, margin to limit, and a concise explanation of outliers. This discipline prevents an attractive nominal plot from being mistaken for a robust design and makes regressions attributable when the implementation, package, firmware, or compiler changes. The review should also record sensitivity to configuration and environmental variation, distinguish average behavior from worst-case tails, and preserve a reproducible baseline for future implementations. Cross-functional sign-off aligns circuit, architecture, firmware, software, package, board, test, and operations owners on the same limits and evidence. Requirements should name the observation point and measurement bandwidth, because the same design can look very different at an internal node, a package pin, or an application boundary. Guard bands must be justified by modeled uncertainty and correlation data rather than inherited without context. Automation should emit both a compact pass or fail summary and enough raw data to reproduce every result. Versioned inputs, deterministic seeds where possible, machine-readable limits, and retained waveforms turn sign-off from a presentation into an auditable engineering process. Corner selection deserves explicit reasoning: independently combining every worst case can be impossible, while checking only named process corners can miss correlated variation. Sensitivity analysis and targeted Monte Carlo runs help direct expensive verification toward the variables that actually control yield and field margin.

<svg viewBox="0 0 960 380" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,sans-serif">
<rect width="960" height="380" rx="12" fill="#1a1a17"/>
<defs><marker id="arrow" markerWidth="8" markerHeight="8" refX="7" refY="4" orient="auto"><path d="M0,0 L8,4 L0,8 Z" fill="#6fafaf"/></marker></defs>
<text x="480" y="30" text-anchor="middle" font-size="16" font-weight="700" fill="#f4f1e8">Ethernet speed evolution and AI leaf-spine fabric</text>
<text x="35" y="75" font-size="10" fill="#c9c3f2">10M</text><line x1="65" y1="71" x2="910" y2="71" stroke="#6fafaf" stroke-width="3" marker-end="url(#arrow)"/><g fill="#2dd4bf"><circle cx="95" cy="71" r="6"/><circle cx="210" cy="71" r="6"/><circle cx="325" cy="71" r="6"/><circle cx="440" cy="71" r="6"/><circle cx="555" cy="71" r="6"/><circle cx="670" cy="71" r="6"/><circle cx="785" cy="71" r="6"/><circle cx="895" cy="71" r="6"/></g><g text-anchor="middle" font-size="9" fill="#f4f1e8"><text x="95" y="95">10M</text><text x="210" y="95">100M</text><text x="325" y="95">1G</text><text x="440" y="95">10G</text><text x="555" y="95">100G</text><text x="670" y="95">200G</text><text x="785" y="95">400G</text><text x="895" y="95">800G</text></g><rect x="330" y="135" width="125" height="45" rx="7" fill="#111318" stroke="#9a8adf"/><text x="392" y="161" text-anchor="middle" font-size="11" fill="#f4f1e8">Spine A</text><rect x="505" y="135" width="125" height="45" rx="7" fill="#111318" stroke="#9a8adf"/><text x="567" y="161" text-anchor="middle" font-size="11" fill="#f4f1e8">Spine B</text><rect x="205" y="235" width="125" height="45" rx="7" fill="#111318" stroke="#2dd4bf"/><text x="267" y="261" text-anchor="middle" font-size="11" fill="#f4f1e8">Leaf 1</text><rect x="418" y="235" width="125" height="45" rx="7" fill="#111318" stroke="#2dd4bf"/><text x="480" y="261" text-anchor="middle" font-size="11" fill="#f4f1e8">Leaf 2</text><rect x="630" y="235" width="125" height="45" rx="7" fill="#111318" stroke="#2dd4bf"/><text x="692" y="261" text-anchor="middle" font-size="11" fill="#f4f1e8">Leaf 3</text><g stroke="#6fafaf" stroke-width="2"><path d="M392 180 L267 235"/><path d="M392 180 L480 235"/><path d="M392 180 L692 235"/><path d="M568 180 L267 235"/><path d="M568 180 L480 235"/><path d="M568 180 L692 235"/></g><g fill="#14312a" stroke="#6fbf6f"><rect x="195" y="320" width="145" height="34" rx="6"/><rect x="408" y="320" width="145" height="34" rx="6"/><rect x="620" y="320" width="145" height="34" rx="6"/></g><g text-anchor="middle" font-size="10" fill="#f4f1e8"><text x="267" y="341">GPU nodes</text><text x="480" y="341">GPU nodes</text><text x="692" y="341">GPU nodes</text></g>
</svg>

Connection to CFS platform. Explore this topic with the relevant CFS architecture, signal-integrity, circuit, timing, power, and system simulators, then follow linked glossary keywords to move from concept to measurable design trade-offs.