High-NA EUV lithography is the next-generation patterning system that increases the numerical aperture of the EUV projection optics from 0.33 to 0.55 — shrinking the minimum printable half-pitch from ~13 nm to ~8 nm in a single exposure. ASML's EXE:5000 (first shipment 2024, ~€350M per tool) is the only High-NA scanner; Intel is the lead customer (Intel 14A, ~2026), with TSMC and Samsung following. High-NA extends EUV lithography one or two more nodes beyond what current 0.33-NA systems can resolve, pushing the industry toward angstrom-scale patterning without falling back to costly multi-patterning.
Resolution — Rayleigh's equation. The minimum resolvable half-pitch (HP) in optical lithography:
$$\text{HP} = k_1 \cdot \frac{\lambda}{\text{NA}}$$
For current EUV ($\lambda$ = 13.5 nm, NA = 0.33, $k_1$ ≈ 0.3–0.4): HP ≈ 12–16 nm. For High-NA ($\lambda$ = 13.5 nm, NA = 0.55, $k_1$ ≈ 0.3–0.4): HP ≈ 7–10 nm. The 67% increase in NA delivers a proportional improvement in resolution — the same physics that drives microscope objectives, now at 13.5 nm wavelength with all-reflective optics in vacuum.
Depth of focus — the trade-off. Increasing NA narrows depth of focus (DoF):
$$\text{DoF} = k_2 \cdot \frac{\lambda}{\text{NA}^2}$$
At 0.55 NA: DoF drops by $(0.55/0.33)^2 \approx 2.8\times$ compared to 0.33 NA — from ~100 nm to ~35–45 nm. This razor-thin focus budget demands: (1) flatter wafers (global planarity <10 nm), (2) ultra-precise wafer stage leveling (real-time topography correction), (3) thinner resist stacks (~20–30 nm), and (4) tighter CMP uniformity across every underlayer.
Anamorphic optics — the enabling innovation. Simply scaling a 0.33-NA lens to 0.55 NA would require mirrors too large to manufacture. ASML's solution: an anamorphic (non-rotationally-symmetric) optical design that magnifies 4× in one axis and 8× in the perpendicular axis. This keeps mirror sizes manageable but means the mask field shrinks from 26×33 mm (standard EUV) to 26×16.5 mm in the scanning direction — exactly half the field area. Consequence: die sizes larger than 26×16.5 mm require field stitching (two exposures bonded at the overlap), which adds complexity and edge-placement error at the stitch boundary.
| Parameter | Current EUV (0.33 NA) | High-NA EUV (0.55 NA) | Impact |
|---|---|---|---|
| Numerical aperture | 0.33 | 0.55 | 67% higher resolution |
| Wavelength | 13.5 nm | 13.5 nm | Same EUV source |
| Min half-pitch (k₁=0.33) | ~13 nm | ~8 nm | Enables 14A / A14 nodes |
| Depth of focus | ~100 nm | ~35–45 nm | 2.8× tighter → thinner resist |
| Mask magnification | 4× (symmetric) | 4× × 8× (anamorphic) | Half field in scan direction |
| Exposure field | 26 × 33 mm | 26 × 16.5 mm | Large dies need stitching |
| Source power needed | 250–500 W | 500–800 W (target) | Higher dose demand |
| Resist thickness | 30–40 nm | 20–30 nm | Thinner → pattern collapse risk |
| Overlay budget | ~2 nm | <1.5 nm | Tighter stage/metrology |
| Throughput target | 150–200 WPH | 150+ WPH (goal) | Must match 0.33 NA economics |
| Tool cost | ~€180M (NXE:3800) | ~€350M (EXE:5000) | 2× cost → must print 2× more layers/tool |
The half-field problem. Because the exposure field is halved in one dimension, any chip larger than ~26×16.5 mm must be exposed in two stitched shots. For AI accelerators (H100 die = 814 mm², MI300X chiplet = ~700 mm²), this means either: (a) redesigning the chip to fit within the half-field (costly), (b) stitching with sub-1 nm overlay accuracy (challenging), or (c) using High-NA only for the most critical layers (metal/via pitches below ~20 nm) while keeping the rest on 0.33-NA EUV or immersion (the expected initial approach).
Resist challenges. Thinner resist (~20–25 nm) with reduced photon shot noise requires higher EUV dose — but EUV source power is finite, so throughput degrades without mitigation. Metal-oxide resists (MOx, e.g. tin-oxide-based inorganic resists) offer 2–3× better EUV absorption than chemically-amplified resists (CAR) at the same thickness, enabling adequate dose at production throughput. Dry-development resists (no wet puddle) reduce pattern collapse in the high-aspect-ratio features that thin resist creates.
Source power. Current EUV sources deliver 250–500 W of in-band 13.5 nm power to the intermediate focus. High-NA needs 500–800 W to maintain throughput at the higher dose demanded by thinner resist and finer features. ASML/Trumpf's tin-droplet laser-produced-plasma (LPP) source is being scaled with higher-repetition-rate CO₂ lasers (~100 kHz) and optimized tin-droplet targeting. Reaching 800 W in-band is the critical path item for High-NA productivity parity with 0.33-NA tools.
<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 460" font-family="system-ui,sans-serif">
<rect width="760" height="460" fill="#1a1a17" rx="12"/>
<text x="380" y="28" fill="#c9c3f2" font-size="15" text-anchor="middle" font-weight="600">High-NA EUV — optical path and resolution scaling</text>
<!-- Left: optical diagram -->
<text x="50" y="55" fill="#8a8a86" font-size="11">EXE:5000 anamorphic optical column</text>
<!-- EUV source -->
<circle cx="80" cy="100" r="20" fill="#4a3a3a" stroke="#e0913a" stroke-width="1.5"/>
<text x="80" y="104" fill="#e0913a" font-size="9" text-anchor="middle">Sn LPP</text>
<text x="80" y="130" fill="#8a8a86" font-size="8" text-anchor="middle">13.5 nm</text>
<!-- Collector mirror -->
<path d="M110,80 Q130,100 110,120" fill="none" stroke="#6fafaf" stroke-width="2.5"/>
<text x="140" y="75" fill="#6fafaf" font-size="8">Collector</text>
<!-- Illuminator -->
<rect x="155" y="85" width="40" height="30" fill="#2a2a3a" stroke="#6f6fbf" stroke-width="1.2" rx="3"/>
<text x="175" y="104" fill="#9a9adf" font-size="8" text-anchor="middle">Illum.</text>
<!-- Mask -->
<rect x="220" y="80" width="60" height="8" fill="#6a6a67" stroke="#afafab" stroke-width="1.2"/>
<text x="250" y="73" fill="#afafab" font-size="9" text-anchor="middle">Reticle (4×/8× mag)</text>
<rect x="220" y="88" width="60" height="4" fill="#4a4a6a"/>
<!-- Projection optics (anamorphic) -->
<ellipse cx="300" cy="140" rx="30" ry="50" fill="none" stroke="#9a8adf" stroke-width="2" stroke-dasharray="4,2"/>
<text x="300" y="200" fill="#9a8adf" font-size="9" text-anchor="middle">Anamorphic</text>
<text x="300" y="213" fill="#9a8adf" font-size="9" text-anchor="middle">projection</text>
<text x="300" y="226" fill="#8a8a86" font-size="8" text-anchor="middle">NA = 0.55</text>
<!-- Beam path -->
<line x1="110" y1="100" x2="155" y2="100" stroke="#e0913a" stroke-width="1" stroke-dasharray="3,2"/>
<line x1="195" y1="100" x2="220" y2="84" stroke="#e0913a" stroke-width="1" stroke-dasharray="3,2"/>
<line x1="250" y1="92" x2="285" y2="120" stroke="#e0913a" stroke-width="1" stroke-dasharray="3,2"/>
<line x1="300" y1="190" x2="300" y2="250" stroke="#e0913a" stroke-width="1.5" marker-end="url(#hnarr)"/>
<!-- Wafer -->
<rect x="260" y="255" width="80" height="12" fill="#6a6a67" stroke="#afafab" stroke-width="1.2" rx="2"/>
<text x="300" y="282" fill="#8a8a86" font-size="9" text-anchor="middle">Wafer (8 nm HP)</text>
<!-- Right: resolution comparison -->
<rect x="400" y="50" width="330" height="180" fill="#1f1f1c" stroke="#3a3a37" stroke-width="1" rx="8"/>
<text x="565" y="75" fill="#c9c3f2" font-size="12" text-anchor="middle" font-weight="500">Resolution scaling (HP = k₁·λ/NA)</text>
<!-- 0.33 NA bar -->
<rect x="430" y="100" width="130" height="28" fill="#4a4a6a" stroke="#6f6fbf" stroke-width="1.2" rx="4"/>
<text x="495" y="118" fill="#d4c8ff" font-size="10" text-anchor="middle">0.33 NA: ~13 nm HP</text>
<!-- Arrow -->
<line x1="565" y1="114" x2="580" y2="114" stroke="#8a8a86" stroke-width="1.5" marker-end="url(#hnarr)"/>
<!-- 0.55 NA bar (smaller = better resolution) -->
<rect x="585" y="105" width="80" height="18" fill="#5a4a8a" stroke="#c9c3f2" stroke-width="1.5" rx="4"/>
<text x="625" y="118" fill="#c9c3f2" font-size="10" text-anchor="middle">0.55 NA: ~8 nm</text>
<!-- DoF comparison -->
<text x="495" y="155" fill="#8a8a86" font-size="10" text-anchor="middle">DoF: ~100 nm</text>
<text x="625" y="155" fill="#e0913a" font-size="10" text-anchor="middle">DoF: ~40 nm</text>
<text x="565" y="175" fill="#8a8a86" font-size="9" text-anchor="middle">2.8× tighter focus → thinner resist, flatter wafers</text>
<!-- Field size comparison -->
<rect x="430" y="185" width="66" height="33" fill="#2a3a2a" stroke="#6fbf6f" stroke-width="1"/>
<text x="463" y="205" fill="#6fbf6f" font-size="8" text-anchor="middle">26×33 mm</text>
<text x="463" y="225" fill="#8a8a86" font-size="7" text-anchor="middle">0.33 NA field</text>
<rect x="530" y="185" width="66" height="17" fill="#3a3a28" stroke="#e8d44d" stroke-width="1"/>
<text x="563" y="197" fill="#e8d44d" font-size="8" text-anchor="middle">26×16.5 mm</text>
<text x="563" y="225" fill="#8a8a86" font-size="7" text-anchor="middle">0.55 NA (half field)</text>
<!-- Bottom: node roadmap -->
<rect x="50" y="300" width="680" height="140" fill="#1f1f1c" stroke="#3a3a37" stroke-width="1" rx="8"/>
<text x="390" y="325" fill="#c9c3f2" font-size="12" text-anchor="middle" font-weight="500">Lithography roadmap — when High-NA enters</text>
<!-- Timeline -->
<line x1="100" y1="370" x2="700" y2="370" stroke="#6f6f6a" stroke-width="1.5"/>
<!-- Nodes -->
<circle cx="150" cy="370" r="5" fill="#6f6fbf"/>
<text x="150" y="360" fill="#6f6fbf" font-size="9" text-anchor="middle">N5/5nm</text>
<text x="150" y="390" fill="#8a8a86" font-size="8" text-anchor="middle">0.33 NA</text>
<text x="150" y="402" fill="#6f6f6a" font-size="7" text-anchor="middle">2020</text>
<circle cx="270" cy="370" r="5" fill="#6f6fbf"/>
<text x="270" y="360" fill="#6f6fbf" font-size="9" text-anchor="middle">N3</text>
<text x="270" y="390" fill="#8a8a86" font-size="8" text-anchor="middle">0.33 NA</text>
<text x="270" y="402" fill="#6f6f6a" font-size="7" text-anchor="middle">2022</text>
<circle cx="390" cy="370" r="5" fill="#9a8adf"/>
<text x="390" y="360" fill="#9a8adf" font-size="9" text-anchor="middle">N2/20A</text>
<text x="390" y="390" fill="#8a8a86" font-size="8" text-anchor="middle">0.33 + EUV DP</text>
<text x="390" y="402" fill="#6f6f6a" font-size="7" text-anchor="middle">2025</text>
<circle cx="510" cy="370" r="6" fill="#c9c3f2"/>
<text x="510" y="356" fill="#c9c3f2" font-size="9" text-anchor="middle" font-weight="600">A14/14A</text>
<text x="510" y="390" fill="#e0913a" font-size="9" text-anchor="middle">High-NA 0.55</text>
<text x="510" y="402" fill="#6f6f6a" font-size="7" text-anchor="middle">2026–27</text>
<circle cx="630" cy="370" r="6" fill="#c9c3f2"/>
<text x="630" y="356" fill="#c9c3f2" font-size="9" text-anchor="middle" font-weight="600">A10</text>
<text x="630" y="390" fill="#e0913a" font-size="9" text-anchor="middle">High-NA + EUV DP</text>
<text x="630" y="402" fill="#6f6f6a" font-size="7" text-anchor="middle">2028+</text>
<!-- Annotation -->
<text x="390" y="430" fill="#d4d4d0" font-size="10" text-anchor="middle">High-NA enables single-exposure at pitches below 20 nm — eliminating EUV double-patterning cost</text>
<defs><marker id="hnarr" markerWidth="6" markerHeight="6" refX="5" refY="3" orient="auto"><path d="M0,0 L6,3 L0,6" fill="none" stroke="#8a8a86" stroke-width="1"/></marker></defs>
</svg>
Economics — the $350M question. A single EXE:5000 costs roughly €350M — nearly twice the NXE:3800 (€180M). To justify the investment, each High-NA tool must process enough wafers at enough layers to amortize its cost over production volume. Intel's calculus: High-NA eliminates the need for EUV double-patterning (which uses two 0.33-NA exposures per layer), so one High-NA shot replaces two 0.33-NA shots at critical metal layers — effectively doubling the throughput per critical layer and justifying the tool premium. The break-even requires High-NA throughput to reach at least 150 WPH (wafers per hour) at production dose.
What High-NA means for AI chip manufacturing. The tightest metal pitches on next-generation AI accelerators (18–20 nm M1 pitch at Intel 14A / TSMC A14) are below what 0.33-NA EUV can resolve in a single exposure. Without High-NA, these layers would require EUV double-patterning — doubling litho cost and halving effective throughput at the most expensive process step. High-NA makes single-exposure patterning at 8–10 nm half-pitch practical, keeping Moore's Law cost scaling alive for the transistor-dense accelerator dies that power frontier AI training.
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