Extrinsic Gettering (EG) is the process of deliberately introducing defects, damage, or high-doping layers on the wafer backside or in other non-critical regions to create gettering sinks that capture metallic impurities — used as a complement to intrinsic gettering or as the primary gettering mechanism when the wafer has insufficient oxygen for IG, when the thermal budget is too low to develop adequate BMDs, or when particularly aggressive contamination control is required for sensitive devices like CMOS image sensors.
What Is Extrinsic Gettering?
- Definition: A gettering approach that relies on externally engineered defect structures — physical damage, deposited polycrystalline layers, or heavily doped diffused regions — placed on the wafer backside or in other sacrificial areas, providing high-density trap sites for metallic impurities that are independent of the wafer's internal oxygen precipitation characteristics.
- Mechanisms: EG works through three complementary mechanisms — relaxation gettering (metals precipitate at damage sites during cooling because their solubility drops below the dissolved concentration), segregation gettering (metals are more soluble in heavily doped or strained regions and partition there), and injection gettering (phosphorus diffusion injects self-interstitials that kick out substitutional metals, mobilizing them for collection).
- Independence from [Oi]: Unlike intrinsic gettering, extrinsic gettering does not depend on the wafer's oxygen concentration — this makes EG essential for float-zone silicon (very low [Oi]) and for processes that cannot tolerate the thermal budget needed to develop oxygen precipitates.
- Methods: Common EG techniques include polysilicon backside seal deposition, backside mechanical damage (sandblasting, laser marking), backside phosphorus or boron diffusion, and backside ion implantation damage.
Why Extrinsic Gettering Matters
- CMOS Image Sensors: Image sensors are extraordinarily sensitive to metallic contamination — a single iron atom in the photodiode depletion region creates a "white pixel" defect visible in dark-frame images. Both IG and EG are typically combined to achieve the extremely low residual contamination levels (below 10^9 atoms/cm^3) that image sensor processes require.
- Float-Zone Wafers: FZ silicon has oxygen concentrations 100x lower than CZ silicon, making intrinsic gettering impossible — EG is the only option for FZ-based processes (certain power devices, radiation detectors, and high-resistivity RF substrates).
- Low Thermal Budget Processes: Advanced nodes with increasingly constrained thermal budgets may not develop sufficient BMD density to getter effectively — extrinsic gettering provides contamination protection independent of the limited thermal exposure.
- Backup Protection: Even fabs with robust IG add EG as a secondary defense layer — the combination provides redundant gettering capacity that protects yield even when individual contamination events exceed the capacity of either technique alone.
How Extrinsic Gettering Is Implemented
- Polysilicon Backside Seal (PBS): A 0.5-1.5 micron undoped polysilicon layer deposited on the wafer backside provides grain boundaries that trap metals — PBS is thermally stable (unlike mechanical damage that can anneal out), compatible with all subsequent thermal processing, and is the premium EG solution for advanced logic wafers.
- Backside Mechanical Damage: Sandblasting, wet abrasive blasting, or controlled scratching of the wafer backside creates a network of dislocations and microcracks that serve as gettering sinks — this low-cost approach is widely used for less demanding applications but generates particles and creates wafer stress asymmetry.
- Phosphorus Backside Diffusion: Heavy phosphorus doping of the wafer backside exploits the 10-100x higher metal solubility in N+ silicon to create a thermodynamic segregation sink — the phosphorus diffusion itself injects silicon self-interstitials that mobilize metals through the kick-out mechanism.
Extrinsic Gettering is the deliberate engineering of defect-rich trap regions on the wafer backside — providing contamination protection that is independent of the wafer's internal oxygen state, compatible with float-zone substrates and low thermal budgets, and deployable as either the primary gettering defense or as a redundant backup to intrinsic gettering in the most contamination-sensitive semiconductor processes.