Fan-Out Panel-Level Packaging (FOPLP) is the advanced semiconductor packaging technology that performs fan-out wafer-level packaging on large rectangular panels (510×515 mm or 600×600 mm) instead of round 300 mm wafers — providing a 3-5× increase in packaging area and corresponding cost reduction per die compared to fan-out wafer-level packaging (FOWLP), making it the most cost-effective approach for high-volume consumer electronics packaging with fine-pitch redistribution layers.
Why Panel-Level
Round wafer (300mm): Area = π×150² = 70,686 mm²
Panel (510×515mm): Area = 510×515 = 262,650 mm² → 3.7× more area!
Panel (600×600mm): Area = 360,000 mm² → 5.1× more area!
More area → more dies processed per run → lower cost per die
| Format | Usable Area | Cost Advantage |
|---|---|---|
| 300mm wafer FOWLP | ~65,000 mm² | Baseline |
| 510×515 mm panel | ~250,000 mm² | ~40-60% lower |
| 600×600 mm panel | ~340,000 mm² | ~50-70% lower |
FOPLP Process Flow
Step 1: Known Good Die (KGD) preparation
- Test and sort dies from silicon wafer
- Place KGD face-down on temporary carrier
Step 2: Reconstitution (Molding)
- Compression mold epoxy around dies → large rectangular panel
- Dies are embedded in mold compound at precise positions
Step 3: RDL (Redistribution Layer) formation
- Dielectric coating (PI or PBO)
- Lithography for via openings
- Copper plating for traces
- Repeat for multiple RDL layers (2-5 layers)
Step 4: Solder ball attachment
- Ball mount on BGA pads
Step 5: Singulation
- Saw or laser cut individual packages from panel
FOPLP vs. FOWLP vs. FC-BGA
| Parameter | FOWLP (wafer) | FOPLP (panel) | FC-BGA (substrate) |
|---|---|---|---|
| Format | 300mm round | 510×515+ mm rect | 510×515+ mm rect |
| RDL L/S | 2/2 µm | 5/5-8/8 µm | 8/8-15/15 µm |
| RDL layers | 3-6 | 2-4 | 4-12 |
| Substrate cost | High | Low | High |
| Throughput | Medium | High | Medium |
| Die shift control | ±2 µm | ±5-10 µm | N/A |
| Applications | Mobile SoC, 5G | IoT, automotive, consumer | CPU, GPU, HPC |
Technical Challenges
| Challenge | Issue | Solution |
|---|---|---|
| Die placement accuracy | ±5-10 µm (worse than wafer) | Adaptive lithography, die shift compensation |
| Panel warpage | Large thin panel warps significantly | Panel materials engineering, process optimization |
| Lithography | No standard panel litho tools (wafer tools are round) | Mask aligner adaptation, direct-write |
| Equipment availability | Less mature ecosystem than wafer-level | Industry investment, standards (SEMI) |
| Yield | Defects scale with area | Inspection, repair |
Industry Players
| Company | Panel Size | Status |
|---|---|---|
| Samsung (SEMCO) | 510×515 mm | Production |
| Daishinku/Nepes | 600×600 mm | R&D/pilot |
| ASE Group | 600×600 mm | Pilot line |
| JCET | 515×510 mm | R&D |
| TSMC | Focus on FOWLP (wafer) | Wafer-level preferred |
Applications
- IoT devices: Low-cost packaging for sensors and MCUs.
- Automotive: Cost-effective packaging for ADAS and powertrain ICs.
- 5G mmWave: Antenna-in-package (AiP) on panel format.
- Consumer electronics: High-volume mobile and wearable packaging.
Fan-out panel-level packaging is the manufacturing paradigm shift from round to rectangular that unlocks dramatic cost reduction for advanced packaging — by leveraging larger processing areas and adapting display-panel manufacturing expertise to semiconductor packaging, FOPLP makes fan-out packaging economically viable for the high-volume consumer and automotive markets that drive the majority of semiconductor unit shipments.
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