<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Fan-out wafer-level packaging: no substrate, RDL straight on the die</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Dies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · The fan-out structure</text><!-- mold + embedded die --><rect x="38" y="116" width="186" height="30" rx="2" fill="#22262b" stroke="#3a3f45"/><rect x="104" y="116" width="54" height="30" rx="2" fill="#1c2733" stroke="#6f8fb0"/><text x="131" y="135" text-anchor="middle" fill="#adb5bd" font-size="10">die</text><text x="70" y="135" text-anchor="middle" fill="#8b949e" font-size="8.5">mold</text><text x="192" y="135" text-anchor="middle" fill="#8b949e" font-size="8.5">mold</text><!-- RDL band --><rect x="38" y="146" width="186" height="18" rx="2" fill="#1c1430" stroke="#6b5fb0"/><g stroke="#b8732e" stroke-width="1"><line x1="118" y1="147" x2="52" y2="163"/><line x1="122" y1="147" x2="74" y2="163"/><line x1="126" y1="147" x2="96" y2="163"/><line x1="131" y1="147" x2="118" y2="163"/><line x1="131" y1="147" x2="140" y2="163"/><line x1="136" y1="147" x2="162" y2="163"/><line x1="140" y1="147" x2="184" y2="163"/><line x1="144" y1="147" x2="206" y2="163"/></g><text x="131" y="159" text-anchor="middle" fill="#c4b5fd" font-size="8">RDL — Cu in polymer</text><!-- solder balls --><g fill="#e0b13a"><circle cx="52" cy="169" r="3"/><circle cx="74" cy="169" r="3"/><circle cx="96" cy="169" r="3"/><circle cx="118" cy="169" r="3"/><circle cx="140" cy="169" r="3"/><circle cx="162" cy="169" r="3"/><circle cx="184" cy="169" r="3"/><circle cx="206" cy="169" r="3"/></g><!-- die-edge markers --><line x1="104" y1="146" x2="104" y2="178" stroke="#586069" stroke-width="0.8" stroke-dasharray="3 2"/><line x1="158" y1="146" x2="158" y2="178" stroke="#586069" stroke-width="0.8" stroke-dasharray="3 2"/><text x="70" y="187" text-anchor="middle" fill="#34d399" font-size="8.5">fan-out</text><text x="192" y="187" text-anchor="middle" fill="#34d399" font-size="8.5">fan-out</text><text x="36" y="214" fill="#adb5bd" font-size="11">A die is re-molded into a wafer.</text><text x="36" y="229" fill="#adb5bd" font-size="11">Copper RDL is built on its face and</text><text x="36" y="244" fill="#adb5bd" font-size="11">fans I/O out past the die edge.</text><text x="36" y="269" fill="#38bdf8" font-size="11" font-weight="700">No package substrate at all —</text><text x="36" y="284" fill="#38bdf8" font-size="11" font-weight="700">RDL replaces it entirely.</text><text x="36" y="309" fill="#8b949e" font-size="10.5">Package height can drop below</text><text x="36" y="323" fill="#8b949e" font-size="10.5">0.5 mm — great for mobile SoCs.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · Chip-first vs chip-last</text><text x="283" y="112" fill="#f0d9b5" font-size="11.5" font-weight="700">Chip-first (RDL last)</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="290" cy="128" r="6.5" fill="#e0b13a"/><text x="290" y="131" text-anchor="middle">1</text><circle cx="290" cy="146" r="6.5" fill="#e0b13a"/><text x="290" y="149" text-anchor="middle">2</text><circle cx="290" cy="164" r="6.5" fill="#e0b13a"/><text x="290" y="167" text-anchor="middle">3</text><circle cx="290" cy="182" r="6.5" fill="#e0b13a"/><text x="290" y="185" text-anchor="middle">4</text></g><text x="302" y="131" fill="#c9d1d9" font-size="9.7">Place dies on a carrier</text><text x="302" y="149" fill="#c9d1d9" font-size="9.7">Mold — reconstituted wafer</text><text x="302" y="167" fill="#c9d1d9" font-size="9.7">Debond the carrier</text><text x="302" y="185" fill="#c9d1d9" font-size="9.7">Build RDL on die face + balls</text><text x="283" y="203" fill="#e0913a" font-size="9.5">Simple RDL — but dies shift in the mold</text><line x1="283" y1="212" x2="477" y2="212" stroke="#30363d"/><text x="283" y="230" fill="#7ee6c0" font-size="11.5" font-weight="700">Chip-last (RDL first)</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="290" cy="246" r="6.5" fill="#34d399"/><text x="290" y="249" text-anchor="middle">1</text><circle cx="290" cy="264" r="6.5" fill="#34d399"/><text x="290" y="267" text-anchor="middle">2</text><circle cx="290" cy="282" r="6.5" fill="#34d399"/><text x="290" y="285" text-anchor="middle">3</text><circle cx="290" cy="300" r="6.5" fill="#34d399"/><text x="290" y="303" text-anchor="middle">4</text></g><text x="302" y="249" fill="#c9d1d9" font-size="9.7">Build RDL on a carrier first</text><text x="302" y="267" fill="#c9d1d9" font-size="9.7">Attach known-good dies</text><text x="302" y="285" fill="#c9d1d9" font-size="9.7">Mold, then debond</text><text x="302" y="303" fill="#c9d1d9" font-size="9.7">Drop balls + singulate</text><text x="283" y="321" fill="#7ee6c0" font-size="9.5">RDL proven first — less die-shift</text><text x="283" y="343" fill="#8b949e" font-size="10">Both skip the substrate; order trades</text><text x="283" y="356" fill="#8b949e" font-size="10">yield against process steps.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Why it wins &amp; hard parts</text><text x="530" y="112" fill="#34d399" font-size="11.5" font-weight="700">Why it wins</text><g fill="#34d399"><circle cx="534" cy="125" r="2.6"/><circle cx="534" cy="140" r="2.6"/><circle cx="534" cy="155" r="2.6"/><circle cx="534" cy="170" r="2.6"/><circle cx="534" cy="185" r="2.6"/></g><text x="544" y="128" fill="#c9d1d9" font-size="10.5">No substrate → package &lt; 0.5 mm</text><text x="544" y="143" fill="#c9d1d9" font-size="10.5">Cheaper — ~50–70% vs substrate</text><text x="544" y="158" fill="#c9d1d9" font-size="10.5">Short RDL → better electrical</text><text x="544" y="173" fill="#c9d1d9" font-size="10.5">Die near board → better thermal</text><text x="544" y="188" fill="#c9d1d9" font-size="10.5">Scales: InFO-PoP, InFO-L</text><line x1="530" y1="200" x2="724" y2="200" stroke="#30363d"/><text x="530" y="220" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="233" r="2.6"/><circle cx="534" cy="248" r="2.6"/><circle cx="534" cy="263" r="2.6"/><circle cx="534" cy="278" r="2.6"/></g><text x="544" y="236" fill="#adb5bd" font-size="10.5">die-shift &amp; placement accuracy</text><text x="544" y="251" fill="#adb5bd" font-size="10.5">reconstituted-wafer warpage</text><text x="544" y="266" fill="#adb5bd" font-size="10.5">RDL yield over a large area</text><text x="544" y="281" fill="#adb5bd" font-size="10.5">thermal for high-power devices</text><text x="530" y="307" fill="#f87171" font-size="10.5" font-weight="700">Warpage and die movement in the</text><text x="530" y="321" fill="#f87171" font-size="10.5" font-weight="700">mold are the yield gate.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">No substrate, RDL on the die</text><text x="36" y="424" fill="#adb5bd" font-size="10">Copper redistribution is built straight</text><text x="36" y="437" fill="#adb5bd" font-size="10">onto the molded die face; the organic</text><text x="36" y="450" fill="#adb5bd" font-size="10">package substrate disappears.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#34d399" font-size="12.5" font-weight="700">Fan-out adds I/O room</text><text x="283" y="424" fill="#adb5bd" font-size="10">Routing past the die edge gives more</text><text x="283" y="437" fill="#adb5bd" font-size="10">balls at board-friendly pitch than</text><text x="283" y="450" fill="#adb5bd" font-size="10">fan-in WLCSP can.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Warpage &amp; die-shift bite</text><text x="530" y="424" fill="#adb5bd" font-size="10">Reconstituted-wafer warpage and die</text><text x="530" y="437" fill="#adb5bd" font-size="10">movement in the mold gate FOWLP</text><text x="530" y="450" fill="#adb5bd" font-size="10">yield.</text></svg>

Fan-Out Wafer-Level Packaging (FOWLP) is the advanced packaging technology that redistributes I/O beyond the die edge by embedding die in molding compound and forming RDL on the reconstituted wafer — enabling 2-10× higher I/O density than traditional WLP, supporting 0.2-0.4mm pitch, integrating multiple die with <100μm spacing, and powering flagship smartphones, AI accelerators, and HPC processors with TSMC InFO, Samsung FOPLP capturing 60-70% of premium mobile market.

FOWLP Architecture and Process:

• Die Placement: pick tested good die from wafer; place face-down on temporary carrier with adhesive; spacing 100-500μm between die; precision ±10μm required
• Molding: compression mold epoxy molding compound (EMC) around die; thickness 100-300μm; covers die backside; creates reconstituted wafer; 300mm format typical
• Carrier Release: remove temporary carrier; expose die face; clean adhesive residue; ready for RDL formation
• RDL Formation: deposit and pattern 2-6 metal layers; line/space 2/2μm to 10/10μm; via diameter 10-30μm; extends beyond die edge (fan-out); enables high I/O count
• Bumping and Singulation: form solder bumps or Cu pillars; saw into individual packages; package size larger than die (fan-out area); typical 1.2-2× die size

FOWLP Variants:

• TSMC InFO (Integrated Fan-Out): chip-first process; RDL on die face; 2-6 RDL layers; used in Apple A-series, M-series processors; 40-50% of FOWLP market
• Samsung FOPLP (Fan-Out Panel-Level Package): panel-based (510×515mm) instead of wafer; higher throughput; lower cost; used in Exynos processors
• Deca M-Series: chip-last process; RDL before die attach; adaptive patterning compensates die placement variation; used by Qualcomm, MediaTek
• ASE FOCoS (Fan-Out Chip-on-Substrate): hybrid approach; FOWLP on substrate; combines benefits of both; used for high-performance applications

Multi-Die Integration:

• Heterogeneous Integration: integrate logic, memory, RF, power management in single package; die spacing 100-500μm; RDL connects die; system-in-package (SiP)
• 2.5D-Like Performance: achieve near-2.5D bandwidth (100-500 GB/s) at lower cost; no silicon interposer; RDL provides die-to-die interconnect
• Memory Stacking: stack HBM or LPDDR on logic die; through-mold vias (TMV) for vertical connection; enables high-bandwidth memory access
• Example: Apple M1 Ultra uses InFO_LSI (locally silicon interconnect) to connect two M1 Max die; 2.5 TB/s bandwidth; seamless integration

RDL Technology:

• Fine-Line RDL: 2/2μm line/space for high-density routing; semi-additive process (SAP); Cu electroplating; 5-10 metal layers typical
• Dielectric: polyimide (PI) or polybenzoxazole (PBO); spin-coat or laminate; thickness 5-15μm per layer; low CTE (<30 ppm/°C) for reliability
• Via Formation: laser drill or photolithography; via diameter 10-30μm; aspect ratio 1:1 to 2:1; Cu fill by electroplating
• Thickness: total RDL stack 50-150μm; thinner than substrate (200-400μm); enables thin packages; critical for mobile devices

Warpage Management:

• Warpage Challenge: CTE mismatch between die (2.6 ppm/°C), mold (8-15 ppm/°C), RDL (17-25 ppm/°C); causes warpage up to 500μm for 300mm wafer
• Mitigation Strategies: balanced RDL design (symmetric metal distribution); low-CTE mold compound; thicker mold (200-300μm); carrier support during processing
• Measurement: shadow moiré, laser scanning measure warpage; <200μm target for assembly; <100μm for fine-pitch bumping
• Impact: excessive warpage causes assembly failures; bump co-planarity issues; yield loss; critical control parameter

Equipment and Process Control:

• Die Bonder: Besi, ASM for high-precision die placement; throughput 5,000-10,000 UPH (units per hour); ±5μm placement accuracy
• Molding: Towa, ASMPT for compression molding; 300mm wafer format; void-free molding critical; cycle time 60-120 seconds
• Lithography: Canon, Nikon i-line or KrF steppers for RDL; overlay ±2-3μm; older generation tools sufficient; cost-effective
• Metrology: KLA, Onto Innovation for overlay, CD, defect inspection; critical for multi-layer RDL; inline monitoring essential

Cost and Performance:

• Cost Position: 20-40% more expensive than standard WLP; 50-70% cheaper than 2.5D with interposer; sweet spot for high-performance mobile
• I/O Density: 500-2000 I/O per package; 5-10× higher than WLP; sufficient for mobile processors, mid-range AI accelerators
• Bandwidth: 50-200 GB/s for single die; 100-500 GB/s for multi-die with short RDL interconnect; competitive with 2.5D for many applications
• Thermal Performance: mold compound has poor thermal conductivity (0.5-1 W/m·K); limits power dissipation; <15W typical; heat spreader or TIM required for higher power

Applications and Market:

• Mobile Processors: Apple A/M-series, Qualcomm Snapdragon, MediaTek Dimensity; 60-70% of premium smartphone market; flagship devices
• AI Accelerators: edge AI chips, mobile AI processors; 5-15W power range; FOWLP provides sufficient I/O and thermal performance
• RF Front-End: integrate PA, LNA, switches, filters; FOWLP enables compact SiP; used in 5G smartphones
• Automotive: ADAS processors, infotainment SoCs; FOWLP provides reliability and integration; growing market

Reliability and Quality:

• Board-Level Reliability: 1000-2000 thermal cycles (-40 to 125°C); underfill required for >10mm packages; comparable to flip-chip BGA
• Moisture Sensitivity: MSL 3-4 typical; mold compound absorbs moisture; baking before assembly; popcorning risk during reflow
• Drop Test: critical for mobile devices; 1.5m drop on concrete; 50-100 drops typical; package design and underfill critical
• Yield: 90-95% package yield typical; lower than traditional packaging; improving with process maturity; defects in RDL, molding main issues

Industry Landscape:

• TSMC InFO: market leader; 40-50% market share; used by Apple, AMD, Broadcom; continuous innovation (InFO_oS, InFO_LSI)
• Samsung FOPLP: panel-level approach; cost advantage; used in Exynos, some Qualcomm; 15-20% market share
• OSATs: Amkor, ASE, JCET offer FOWLP services; licensed technologies or proprietary; combined 30-40% market share
• Market Size: $3-5B annually; growing 15-20% per year; driven by mobile, AI, automotive; expected to reach $10B by 2028

Future Developments:

• Finer Pitch: 0.15-0.2mm bump pitch for higher I/O; requires advanced RDL (1/1μm line/space); enabling 3000-5000 I/O packages
• Thicker Mold: 400-600μm for better thermal performance; enables higher power devices (20-30W); challenges in warpage control
• Hybrid Bonding: combine FOWLP with hybrid bonding for ultra-high bandwidth; 10-20μm pitch die-to-die connection; next-generation integration
• Panel-Level: 600×600mm panels for higher throughput; 30-50% cost reduction potential; Samsung leading; industry adoption expected 2025-2027

Fan-Out Wafer-Level Packaging is the technology that bridges the gap between traditional packaging and advanced 2.5D/3D — by enabling high I/O density, multi-die integration, and heterogeneous integration at 50-70% lower cost than interposer-based approaches, FOWLP has become the packaging of choice for premium mobile processors and mid-range AI accelerators, powering billions of devices worldwide.