Fin Depopulation and Active Area Patterning is the process of selectively removing unwanted fins from a continuous fin array fabricated by spacer-based multi-patterning, defining the active transistor regions and providing electrical isolation between devices while maintaining the structural regularity required for downstream process uniformity in FinFET and nanosheet architectures.

Fin Array Formation and the Need for Depopulation:

• Regular Fin Array: SADP or SAQP patterning creates a continuous array of fins at fixed pitch (25-30 nm at N5/N3) across the entire active area—individual device widths are defined by which fins remain active
• Drive Current Quantization: FinFET drive current is quantized in units of single fins—a 3-fin device has 50% more current than a 2-fin device, with no intermediate values available
• Dummy Fins: fins at array edges or between devices that are not connected to source/drain or gate are "dummy" fins—they must be removed or electrically isolated to prevent parasitic leakage
• Isolation Requirement: fin-to-fin leakage between adjacent devices must be <10 fA/µm at operating voltage—achieved through complete fin removal or dielectric fill between active and dummy fins

Fin Cut (Depopulation) Process:

• Lithography: EUV single-exposure patterning defines fin cut regions with 12-18 nm minimum feature size—overlay to underlying fin array must be <2 nm
• Cut Etch: anisotropic RIE removes exposed Si fins using HBr/Cl₂/O₂ chemistry, stopping on STI oxide with >30:1 selectivity—etch must remove fins completely to STI level without attacking adjacent retained fins
• Fin Stub Control: residual fin material (stubs) remaining after cut etch must be <2 nm tall to prevent leakage paths—requires precise endpoint detection and over-etch control
• Sidewall Protection: SiN spacer on retained fin sidewalls protects against lateral etch—spacer integrity requires passivating chemistry with <0.5 nm/min lateral etch rate

Active Area Patterning Approaches:

• Cut-First: fin cuts performed on mandrel before spacer deposition—cut shapes modify mandrel pattern, and spacers form only on retained mandrel features
• Cut-Last: fin cuts performed after final fin etch—allows full fin array to benefit from SADP/SAQP uniformity before selective removal
• Block Lithography: instead of cutting individual fins, block mask exposes groups of fins for removal—relaxes CD requirements but wastes lithographic resolution
• Hybrid Approach: coarse fin cuts by 193i block mask, fine single-fin cuts by EUV—optimizes cost by limiting expensive EUV exposure to critical features only

Integration with Nanosheet Transistors:

• Superlattice Cut: fin depopulation in nanosheet architecture must cut through 80-120 nm tall Si/SiGe superlattice stacks—higher aspect ratio (4:1 to 6:1) than FinFET fin cut
• Si/SiGe Etch Uniformity: alternating Si and SiGe layers etch at different rates, creating scalloped sidewall profiles—etch chemistry must equalize rates to achieve smooth vertical profile with <1 nm scalloping
• Channel Release Compatibility: fin cut surfaces must be compatible with subsequent SiGe sacrificial layer removal—cut fill dielectric must resist HCl-based channel release etch

Process Control and Metrology:

• Overlay Metrology: in-die overlay targets measure fin cut placement relative to fin array—YieldStar or µDBO techniques achieve <0.3 nm measurement uncertainty
• Fin Height Uniformity: post-cut fin height across retained fins must be uniform to ±1 nm—variation causes Vt non-uniformity of 5-10 mV/nm of fin height variation
• Defect Inspection: unremoving fin stubs and partially cut fins are killer defects—high-resolution e-beam inspection at 3-5 nm sensitivity required after cut etch and before STI fill
• CD-SEM Monitoring: fin width and spacing measured by CD-SEM with <0.3 nm precision—pitch walking from SADP must be tracked through cut process to ensure it doesn't worsen

Yield Implications:

• Cut Miss: failure to completely remove a dummy fin creates parasitic transistor—yield loss depends on defective fin location relative to active devices
• Excessive Etching: over-etch during fin removal damages adjacent active fins, reducing fin height and degrading drive current by 3-5% per nm of height loss
• STI Recess: fin cut etch can recess STI oxide between remaining fins, changing fin effective height—STI recess variation must be <1 nm across the die

Fin depopulation and active area patterning is the critical process bridge between regular array patterning and functional circuit definition, where the precision of fin removal and isolation directly determines the transistor density, leakage current, and parametric yield that define each technology node's value proposition.