FinFET (Fin Field-Effect Transistor) is the 3D transistor architecture that replaced planar MOSFETs at the 22nm node, using a vertical fin channel wrapped by the gate on three sides for superior electrostatic control. Structure: thin silicon fin (5-7nm wide) rises vertically from substrate, gate wraps around three sides (tri-gate), providing excellent control over channel. Key parameters: fin pitch (25-30nm at 7nm node), fin height (40-50nm), fin width (5-7nm), number of fins per transistor (determines drive strength). Advantages over planar: (1) Better electrostatics—gate controls channel from three sides, reducing short-channel effects; (2) Lower leakage—improved subthreshold slope and DIBL; (3) Higher drive current—more channel width per layout area; (4) Continued voltage scaling—better control enables lower operating voltage. FinFET generations: (1) 22/20nm—first generation (Intel 22nm tri-gate, 2012); (2) 16/14nm—optimized fins, industry-wide adoption; (3) 10/7nm—taller fins, tighter pitch, higher performance; (4) 5nm—near physical limits of FinFET scaling. Manufacturing challenges: (1) Fin patterning—SADP/SAQP for tight pitch; (2) Fin profile—vertical, uniform fins across wafer; (3) Gate formation—conformal high-κ/metal gate around fin; (4) Epitaxial source/drain—SiGe (PMOS) or Si:P (NMOS) grown on fins; (5) Contact—wrapping contact around fins and S/D epi. Quantized width: drive strength comes in discrete fin increments (can't add half a fin). Successor: Gate-All-Around (GAA) nanosheet/nanowire transistors at 3nm and beyond, where gate wraps all four sides of stacked horizontal channels for even better electrostatic control.