Chip Floorplanning is the early-stage physical design process that defines the chip's physical organization — determining die size, placing hard macros (memories, PLLs, ADCs, I/O pads), partitioning power domains, defining clock regions, and establishing the top-level routing topology — where decisions made during floorplanning propagate through every subsequent design step and can improve or destroy timing closure, power integrity, and routability.

Why Floorplanning Matters

A bad floorplan cannot be fixed by downstream optimization. If two blocks that communicate intensively are placed on opposite sides of the die, no amount of buffer insertion or routing optimization can recover the wire delay penalty. Conversely, a well-crafted floorplan places communicating blocks adjacent, minimizes critical path wire lengths, and provides sufficient routing channels to avoid congestion — making timing closure straightforward.

Floorplanning Decisions

1. Die Size Estimation: Total cell area + macro area + routing overhead (typically 1.4-2.0x cell area, depending on metal layer count and routing density) + I/O ring area. Die size directly impacts cost (die per wafer) and yield (larger die = lower yield). 2. Macro Placement:

• Memories (SRAMs): Largest macros, often consuming 30-60% of die area. Placed to minimize data path length to the logic that accesses them. Aligned to power grid and clock tree topology.
• Analog/Mixed-Signal: PLLs, ADCs, DACs are sensitive to digital switching noise. Placed in quiet corners of the die with dedicated power supplies and guard rings.
• I/O Pads: Placed on the die periphery (wire-bond) or in an array (flip-chip). I/O pad order is constrained by package pin assignment and board-level routing.

3. Power Domain Partitioning: Blocks with different supply voltages or power-gating requirements are placed in separate physical power domains. Each domain requires its own power switches (header/footer cells), isolation cells at domain boundaries, and level shifters. 4. Clock Region Planning: Define which clock domains cover which physical regions. Minimize clock crossings between regions to reduce CDC complexity. 5. Routing Channel Planning: Reserve routing channels between macros for signal and power routing. Insufficient channels create routing congestion that may be unfixable without moving macros.

Floorplan Evaluation Metrics

• Wirelength Estimate: Total estimated wire length based on half-perimeter bounding box (HPWL) of each net in the initial placement.
• Congestion Map: Routing demand vs. supply per routing tile. Hotspots indicate potential DRC-failing or timing-impacting regions.
• Timing Feasibility: Estimated path delays based on macro-to-macro distances and wire delay models.
• Power Integrity: IR-drop estimation based on the preliminary power grid and macro current profiles.

Floorplanning is the architectural blueprint of the physical chip — the strategic decisions that determine whether the downstream place-and-route flow converges to a timing-clean, DRC-clean, power-clean design, or spirals into an unresolvable mess of violations.