The forksheet transistor is a gate-all-around (GAA) family architecture that replaces each conventional nanosheet's open trench with a vertical dielectric wall running down the middle, so that the N and PMOS sheet stacks share a single fork-shaped trench yet remain physically isolated by the wall. This single change decouples device width from fin pitch, because each sheet stack no longer needs its own separately spaced trench, and it allows the N and P gate stacks to be processed and work-function-tuned independently even though they sit only a wall's width apart. Compared with a conventional GAA nanosheet, the forksheet reduces n-to-p separation and area per bit, but it introduces asymmetric dielectric-wall process steps, sheet-clipping and wall-etch controllability challenges, and new co-optimization demands on the metal stack and local routing that a symmetric nanosheet trench never had to solve.

The dielectric wall is the single structural feature that defines the forksheet architecture. Formed from silicon nitride or SiBCN and typically 3 nm wide with an aspect ratio near 8:1 relative to the sheet stack height, the wall is deposited and etched into the fork-shaped trench before the sacrificial SiGe/Si superlattice is grown on either side. Because the wall physically separates the NMOS and PMOS half-trenches from the earliest stack formation step, it removes the isolation spacer that a conventional nanosheet would otherwise need between adjacent N and P devices, recovering several nanometers of pitch that the spacer previously consumed.

Decoupling device width from fin pitch is the forksheet's core electrical and layout benefit. In a conventional GAA nanosheet, sheet width is bounded by how much lateral space is available within a single fin-pitch trench shared implicitly with the neighboring device; in a forksheet, each half of the fork can be widened independently up to the wall, since the wall — not the neighboring device's trench — sets the boundary. This lets designers tune NMOS and PMOS sheet widths asymmetrically for drive-strength balancing without having to widen the whole cell, a degree of freedom conventional nanosheets do not offer.

Sheet clipping is the process step that shapes each half-stack against the wall and is unique to forksheet integration. After the SiGe/Si superlattice is grown across the full fork trench, an asymmetric etch clips each sheet back to the wall boundary on one side while leaving the opposite, device-facing edge untouched, defining the final sheet width for that half of the fork. Because this clip step must stop cleanly at the wall without undercutting it or leaving residual sheet material, wall-etch selectivity and clip-etch endpoint control are two of the tightest process windows in the entire forksheet flow.

Clip-etch selectivity between the sheet material and the wall dielectric must exceed roughly 30:1 to avoid measurable wall erosion. If the etch that shapes each sheet's outer edge also attacks the adjacent wall surface, the wall narrows below its 3 nm target and its isolation margin degrades exactly where it matters most, at the boundary the two polarities share. Because this etch runs immediately adjacent to the wall on every sheet in the stack, selectivity drift of even a few percent compounds across a 3–5 sheet stack into a measurable width error by the top sheet.

Independent N/P work-function tuning becomes practical once the wall removes cross-talk between adjacent trenches. In a shared or narrowly spaced nanosheet trench, work-function metal deposited for one polarity can contaminate or interact with the adjacent polarity's gate stack unless carefully sequenced; the forksheet wall acts as a physical barrier during metal gate patterning, letting the NMOS side receive a TiAlC-based low-Φm fill near 4.1 eV and the PMOS side a TiN-based fill near 5.1 eV with less risk of cross-contamination at the boundary. This is a direct manufacturing benefit of the wall beyond its role in setting pitch.

Lithographic overlay between the work-function metal patterning step and the wall itself must be held to a fraction of the wall's own width. Because the wall is only 3 nm wide, an overlay error of even 1 nm during metal patterning can leave one polarity's fill metal encroaching on the other side of the wall, which is precisely the cross-contamination the wall was introduced to prevent. Overlay budgets for this step are therefore among the tightest in the entire forksheet mask set, tighter than most contact or via layers at the same node.

The electrostatics of the individual transistor are unchanged by the wall, which is what makes the forksheet a pitch and integration play rather than a device-physics play. Each half of the fork is still a gate-all-around nanosheet with the gate wrapping the channel on all four sides, so effective gate length of 12–15 nm, subthreshold swing below 70 mV/decade, and DIBL below 30 mV/V are the same targets a conventional GAA device carries. $V_t \approx \Phi_m - \Phi_s$ still governs threshold voltage per sheet stack exactly as it would in an isolated nanosheet, confirming that the wall changes layout and process, not the channel's fundamental electrostatics.

forksheet fabrication flow ──▶ wall-first integration
  fork-trench etch + dielectric wall fill
       │      SiN/SiBCN · 3 nm wide · 8:1 aspect ratio
       │
       ├─▶ SiGe/Si superlattice epitaxy across full trench
       │      6 nm sheet thickness · both N/P sides grown together
       │
       ├─▶ asymmetric sheet clipping to wall boundary
       │      clip-etch endpoint control · no wall undercut
       │
       ├─▶ channel release (sacrificial SiGe etch)
       │      independent N/P half-trenches
       │
       ├─▶ independent N/P work-function metal fill
       │      TiAlC (NMOS ≈4.1 eV) / TiN (PMOS ≈5.1 eV)
       │
       └─▶ contact + local routing at compressed n-p pitch
              ≈30 nm n-p spacing · 10–15 percent cell area gain

Equivalent oxide thickness and metal-fill budget inside the narrowed half-trench are tighter than in a conventional nanosheet because the wall consumes lateral space that would otherwise be available for gate metal. A typical forksheet stack still targets an EOT near 1.2 nm with a 2 nm bottom oxide and 5 nm of work-function and fill metal per side, but because the wall claims 3 nm of the trench width outright, the remaining metal-fill window is narrower than in an equivalent-width conventional nanosheet, making void-free metal fill inside each half-trench a harder target to hit as the node scales.

Contact resistivity targets do not relax to compensate for the narrower metal-fill window, which keeps pressure on the fill metal choice. A specific contact resistivity below 1×10⁻⁹ Ω·cm² is still expected of a forksheet contact stack despite the reduced lateral room for fill metal, so foundries lean on the same ruthenium and cobalt fill options being qualified for conventional GAA nanosheets rather than accepting a resistivity penalty as the price of the wall's area benefit.

Mechanical stability of the thin dielectric wall under repeated thermal cycling is a reliability question distinct from anything a conventional nanosheet has to answer. The wall must survive the same high-temperature anneal steps as the rest of the gate stack — commonly in the 900–1000 °C range during activation anneals prior to metal gate formation — without cracking, delaminating, or shifting position relative to the sheet stacks on either side, since even a sub-angstrom lateral shift changes the effective width available to each half-trench. Thermal-mechanical qualification of the wall material is therefore run alongside the standard electrical qualification before a forksheet process is released to volume.

The forksheet concept originated in pre-competitive research rather than inside a single foundry's proprietary roadmap. imec first proposed and demonstrated the forksheet architecture in device papers presented in the late 2010s, positioning it explicitly as a follow-on to GAA nanosheets for extending n-to-p scaling once the nanosheet trench itself became the pitch-limiting feature. That imec origin is why forksheet process modules are frequently described in roadmap literature relative to a shared pre-competitive baseline before each foundry adapts the wall material, aspect ratio, and clip process to its own integration scheme.

The forksheet's ultimate significance is that it treats n-to-p spacing as a solvable process-integration problem rather than an inherent geometric limit of the GAA architecture. Every gain — the 20 nm of recovered separation, the 10–15 percent cell-area reduction, the cleaner independent work-function tuning — traces back to one new unit process, the dielectric wall, and every new risk — wall aspect ratio, sheet-clipping endpoint control, thermal-mechanical wall stability — traces back to that same feature. Read forksheet transistor architecture through a coupled-systems lens: the wall, the sheet-clipping etch, the independent N/P metal fill, and the compressed local routing do not scale independently, so the architecture only delivers its area benefit when all four are qualified together against the same electrostatic and reliability targets a conventional GAA nanosheet already had to meet.

Appendix: Process Control and Metrology Reference

Wall dimension metrology depends on cross-sectional and tomographic techniques capable of resolving sub-nanometer features buried inside the trench. Transmission electron microscopy cross-sections and X-ray-based critical-dimension metrology are used in development to confirm wall width, height, and sidewall angle, since a 0.5 Å drift in sidewall roughness can seed a void that only becomes electrically visible after gate metal fill. Production fabs rely on faster in-line scatterometry once the correlation between optical signature and wall geometry has been calibrated against these reference techniques.

Qualification of a new wall material or clip-etch recipe runs across many lots before it is released to a multi-Vt library, mirroring the qualification discipline used for any new gate-stack unit process. A candidate wall material is evaluated for etch selectivity, fill void rate, and thermal-mechanical stability across dozens of wafers spanning multiple lots, because a recipe with an acceptable mean wall width but excessive lot-to-lot spread will show up as intermittent n-p leakage or Vt drift only after volume ramp, not in early characterization.

Academic groups continue to study wall material alternatives and clip-etch chemistries that could widen the forksheet's process window at future nodes. Research at MIT, Stanford, and UC Berkeley on low-k dielectric wall candidates and on selective etch chemistries for sheet clipping periodically feeds new options into foundry evaluation pipelines, motivated by the same aspect-ratio and endpoint-control challenges that make the wall the hardest single feature in the current forksheet flow.