Forksheet Transistor Technology

# Forksheet Field-Effect Transistors (Forksheet FET): Architecture, Scaling & Physics

The Forksheet Field-Effect Transistor (Forksheet FET) is an advanced Gate-All-Around (GAA) logic architecture pioneered by the Interuniversity Microelectronics Centre (imec) to extend horizontal nanosheet scaling beyond the 2 nm node into the sub-2 nm (1.4 nm / A14) generation. Developed as a natural evolutionary bridge between conventional horizontal GAA nanosheets and complex vertically stacked Complementary FETs (CFET), the Forksheet FET inserts a self-aligned dielectric wall ($\text{SiN}$ or low-k $\text{SiO}_2$, thickness $T_{wall} \approx 15\text{ to }20\,\text{nm}$) between adjacent nMOS and pMOS nanosheet stacks *prior* to gate patterning.

In conventional GAA nanosheet technology, the physical separation between nMOS and pMOS devices ($S_{N-P}$) is constrained to $\ge 50\,\text{nm}$ due to the overlay margins required for lithographic patterning and selective wet/dry chemical etching of dual workfunction metal (WFM) gate stacks. The Forksheet dielectric wall physically partitions the nMOS and pMOS cavities, collapsing the N-to-P space from $50\,\text{nm}$ down to $\le 17\,\text{nm}$. This structural reduction slashes standard cell track height from $5.0\text{T}$ ($125\,\text{nm}$) down to $4.3\text{T}$ or $4.0\text{T}$ ($96\,\text{nm}$), achieving a direct $20\%\text{ to }23\%$ standard cell silicon area scaling while reducing parasitic gate capacitance by $15\%\text{ to }20\%$.

Standard Cell Scaling: Conventional GAA vs. Forksheet FET comparison of nMOS-to-pMOS space (S_N-P), cell track height, and layout density 1. CONVENTIONAL GAA NANOSHEET (5.0T CELL) Standard Cell Height: 5.0T (125 nm) pMOS GAA Nanosheets Wide N-to-P Space: S_N-P ≥ 50 nm Lithography overlay margin for dual-WFM wet etch chemical boundary clearance nMOS GAA Nanosheets • N-to-P Separation: 50 nm (Litho Limited) • Cell Track Height: 5.0T (125 nm) • Parasitic Cap (C_gg): Baseline (1.0×) 2. FORKSHEET FET ARCHITECTURE (4.3T CELL) Standard Cell Height: 4.3T (96 nm) → -20% Area Dielectric Wall (17nm) pMOS Tri-Gate nMOS Tri-Gate • N-to-P Separation: 17 nm (Self-Aligned Wall) • Standard Cell Height: 4.3T (96 nm) [-20% to -23% Area] • Gate Capacitance (C_gg): -17% Reduction (No inner gate) • Self-Aligned Dual WFM: Wall acts as natural etch-stop • Speed / Power Benefit: +12% Frequency @ matched power

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## 1. Physical Principle & Structural Mechanics of the Dielectric Wall

The defining architectural feature of the Forksheet FET is the insertion of a high-aspect-ratio, chemical-resistant dielectric wall between the complementary transistor pairs before the replacement metal gate (RMG) process sequence.

### 1.1 Structural Decomposition
Unlike standard GAA nanosheets where all four sides of each sheet are enveloped by the gate electrode, the Forksheet nanosheet stack abuts the dielectric wall along its interior vertical edge:
1. Tri-Gate Electrostatic Envelope: The gate electrode wraps around only three surfaces of each nanosheet—the top horizontal face, the bottom horizontal face, and the outer vertical sidewall.
2. Dielectric Wall Material Properties:
- Composed of low-k $\text{SiO}_2$ or low-stress silicon nitride ($\text{SiN}_x$), occasionally engineered with atomic layer deposited $\text{SiOCN}$ or $\text{SiC}$ liners.
- Thickness: $T_{wall} = 15\text{ to }20\,\text{nm}$.
- Height: Extends continuously from the shallow trench isolation (STI) base to above the topmost nanosheet layer ($H_{wall} \approx 100\text{ to }120\,\text{nm}$).
3. Self-Aligned Dual Workfunction Metal (WFM) Partitioning:
- In conventional GAA, patterning p-type WFM (e.g., $\text{TiN}$) and n-type WFM (e.g., $\text{TiAlC}$) requires depositing the p-WFM, spinning a photoresist mask, aligning lithography across the tight N-to-P gap, and wet-etching the p-WFM from the nMOS side. The overlay error budget and chemical capillary wet-etch pullback require a physical spacing of at least $50\,\text{nm}$.
- In the Forksheet FET, the dielectric wall serves as an impenetrable physical barrier. The p-WFM is selectively etched back using the dielectric wall as a self-aligned mechanical etch-stop, completely eliminating lithographic overlay margins between nMOS and pMOS.

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## 2. Quantitative Modeling: Area Reduction & Capacitance Physics

Forksheet Parasitic Capacitance & Ring Oscillator Scaling gate capacitance breakdown (C_gg) and propagation delay comparison across cell tracks GATE CAPACITANCE REDUCTION (C_gg) Inner Sidewall Eliminated! Zero inner gate fringing cap Effective Gate Capacitance Formulation: C_gg,GAA = C_ch(2W + 2T) + 2C_fringe C_gg,Fork = C_ch(2W + T) + C_fringe,outer Total Net Capacitance Reduction: -17% Lowers dynamic power consumption: P_dyn = α · C_load · V_DD² · f RO STAGE DELAY vs. STANDARD CELL TRACKS 14 ps 12 ps 10 ps 8 ps 6 ps 6.0T 5.0T 4.3T 3.5T GAA Nanosheet (Cannot scale < 5.0T) Forksheet FET -30% Delay @ 4.3T Standard Cell Track Height (T) →

### 2.1 Standard Cell Scaling Formulation
Standard cell area ($A_{cell}$) in digital CMOS is determined by cell track height ($H_{cell}$) and contacted poly pitch ($\text{CPP}$):

$$A_{cell} = H_{cell} \times (\text{CPP} \times N_{gates})$$

Where $H_{cell} = N_{tracks} \times M_{pitch}$ ($M_{pitch}$ is the tightest metal layer routing pitch, typically $24\text{ to }28\,\text{nm}$). In a 5.0T GAA standard cell:

$$H_{cell,GAA} = 2 \cdot W_{ns} + S_{N-P} + 2 \cdot S_{margin}$$

Substituting realistic dimensions for a 2nm GAA technology ($W_{ns} = 30\,\text{nm}$, $S_{N-P} = 50\,\text{nm}$, and boundary margins $S_{margin} = 7.5\,\text{nm}$):

$$H_{cell,GAA} = 2(30) + 50 + 15 = 125\,\text{nm} \quad (\approx 5.0\,\text{T})$$

If logic designers attempt to shrink a conventional GAA cell to $4.3\text{T}$ ($H_{cell} \approx 96\,\text{nm}$) while maintaining $S_{N-P} = 50\,\text{nm}$, the allowable nanosheet width collapses to:

$$W_{ns} = \frac{96 - 50 - 15}{2} = 15.5\,\text{nm}$$

At $W_{ns} \approx 15\,\text{nm}$, drive current degrades drastically, ruining cell delay. In contrast, the Forksheet FET replaces the $50\,\text{nm}$ gap with a $17\,\text{nm}$ dielectric wall:

$$W_{ns,Forksheet} = \frac{96 - 17 - 15}{2} = 32\,\text{nm}$$

The Forksheet architecture preserves wide, high-current nanosheet channels ($W_{ns} > 30\,\text{nm}$) inside an ultra-dense $4.3\text{T}$ standard cell footprint, delivering an uncompromising $23\%$ net area reduction with zero drive-strength penalty.

### 2.2 Parasitic Capacitance & Switching Energy Physics
The total input gate capacitance of a field-effect transistor consists of channel inversion capacitance ($C_{channel}$) and inner/outer fringing capacitances ($C_{fringe}$):

$$C_{gg} = C_{channel} + C_{fringe,outer} + C_{fringe,inner}$$

In a 4-sided GAA nanosheet, gate electrodes surround all four surfaces:

$$C_{channel,GAA} = \frac{\epsilon_{ox}}{\text{EOT}} \cdot L_g \cdot (2 W_{ns} + 2 T_{ns})$$

In a Forksheet FET, the inner sidewall is replaced by the dielectric wall. The tri-gate channel capacitance is:

$$C_{channel,Forksheet} = \frac{\epsilon_{ox}}{\text{EOT}} \cdot L_g \cdot (2 W_{ns} + T_{ns})$$

Furthermore, the physical presence of the dielectric wall eliminates the inner gate-to-source and gate-to-drain overlap capacitances. TCAD simulations by imec confirm an overall $15\%\text{ to }20\%$ reduction in total gate capacitance ($C_{gg}$). Because dynamic switching power scales quadratically with voltage and linearly with load capacitance:

$$P_{dynamic} = \alpha \cdot C_{load} \cdot V_{DD}^2 \cdot f$$

The Forksheet FET achieves a $12\%\text{ to }16\%$ reduction in active dynamic energy at matched operating frequency, or conversely, a $10\%\text{ to }15\%$ ring oscillator speedup at matched power.

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## 3. Forksheet Process Integration Sequence

Fabricating a Forksheet FET leverages existing GAA nanosheet fab infrastructure while adding the dielectric wall patterning module:

+----------------------------------------------------------------------------------------------------+
|                                  FORKSHEET UNIT PROCESS SEQUENCE                                   |
+----------------------+-------------------------------------+---------------------------------------+
| PROCESS STEP         | KEY TOOLS & CHEMISTRY               | PHYSICAL FUNCTION                     |
+----------------------+-------------------------------------+---------------------------------------+
| 1. Superlattice Epi  | RP-CVD @ 600°C; Si/Si₀.₇Ge₀.₃       | Alternating channel and sacrificial   |
|                      | 3-sheet stack on 300mm bulk Si      | layers with matched lattice constant  |
+----------------------+-------------------------------------+---------------------------------------+
| 2. Wall Trench Etch  | EUV Litho (0.33 NA, λ = 13.5 nm);   | Anisotropic deep trench etch cutting  |
|                      | Cryogenic RIE (-60°C, HBr/Cl₂/O₂)   | between nMOS and pMOS sheet pairs     |
+----------------------+-------------------------------------+---------------------------------------+
| 3. Wall Dielectric   | Thermal ALD SiO₂ or SiN (k = 4-7);  | Fills high-aspect-ratio trench;       |
|    Deposition & CMP  | High-selectivity Chemical Mech Polish| creates planarized dielectric wall    |
+----------------------+-------------------------------------+---------------------------------------+
| 4. Inner Spacer Rec  | Vapor-phase selective SiGe etch;    | Self-aligned lateral cavities flanking|
|                      | Low-k SiBCN ALD fill + etchback     | the sheets, bounded by the wall       |
+----------------------+-------------------------------------+---------------------------------------+
| 5. S/D Epitaxy       | In-situ doped Si:P (nMOS) and       | Faceted source/drain stressor blocks  |
|                      | SiGe:B (pMOS) selective CVD epitaxy | directly anchored to outer sidewalls  |
+----------------------+-------------------------------------+---------------------------------------+
| 6. Sheet Release     | Vapor HCl etching of SiGe;          | Exposes 3 sides of Si sheets; inner   |
|                      | Ultra-high selectivity > 250:1      | edges remain anchored to the wall     |
+----------------------+-------------------------------------+---------------------------------------+
| 7. Self-Aligned WFM  | Atomic Layer Deposition HKMG;       | Dielectric wall acts as vertical etch |
|    Patterning        | Wet-strip p-WFM without photo mask  | stop, separating n-WFM from p-WFM     |
+----------------------+-------------------------------------+---------------------------------------+

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## 4. Architectural Comparison: FinFET, GAA Nanosheet, Forksheet, and CFET

+----------------------------------------------------------------------------------------------------+
|                                ADVANCED LOGIC ARCHITECTURAL SPECTRUM                               |
+----------------------+-------------------+--------------------+------------------+-----------------+
| PARAMETER            | 5nm / 4nm FINFET  | 3nm / 2nm GAA      | 1.4nm FORKSHEET  | 1nm / A10 CFET  |
+----------------------+-------------------+--------------------+------------------+-----------------+
| Gate Topology        | 3-sided tri-gate  | 4-sided full wrap  | 3-sided tri-gate | Dual 4-sided    |
|                      | around tall fin   | around nanosheets  | abutting wall    | vertically stack|
+----------------------+-------------------+--------------------+------------------+-----------------+
| N-to-P Spacing (Sn-p)| 45 to 55 nm       | 50 to 60 nm        | 15 to 20 nm      | 0 nm            |
|                      | (Litho limited)   | (WFM clearance)    | (Dielectric wall)| (3D Stacked)    |
+----------------------+-------------------+--------------------+------------------+-----------------+
| Cell Track Height    | 6.0T to 5.5T      | 5.0T to 4.5T       | 4.3T to 4.0T     | 3.5T to 3.0T    |
| (Cell Height H_cell) | (140 to 130 nm)   | (125 to 110 nm)    | (96 to 90 nm)    | (75 to 65 nm)   |
+----------------------+-------------------+--------------------+------------------+-----------------+
| Gate Cap (C_gg)      | High (Fringing)   | Baseline (1.0×)    | Low (-17% C_gg)  | Moderate (3D)   |
+----------------------+-------------------+--------------------+------------------+-----------------+
| Fab Complexity       | Moderate          | High               | Moderate-High    | Extremely High  |
|                      | (Baseline)        | (+20% mask layers) | (+12% vs. GAA)   | (+45% vs. GAA)  |
+----------------------+-------------------+--------------------+------------------+-----------------+
| Target Node Window   | Production 2018-24| Production 2022-26 | Target 2026-28   | Target 2028-32  |
|                      | (Mature)          | (TSMC N2, SF3)     | (imec / A14)     | (A10 and beyond)|
+----------------------+-------------------+--------------------+------------------+-----------------+

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