<svg xmlns="http://www.w3.org/2000/svg" viewBox="0 0 760 470" font-family="Segoe UI,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Fan-out wafer-level packaging: no substrate, RDL straight on the die</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Dies re-molded into a wafer; copper RDL fans I/O out past the die edge — thinner and cheaper than a package substrate</text><!-- ===== PANEL 1 ===== --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="36" y="92" fill="#38bdf8" font-size="14" font-weight="700">1 · The fan-out structure</text><!-- mold + embedded die --><rect x="38" y="116" width="186" height="30" rx="2" fill="#22262b" stroke="#3a3f45"/><rect x="104" y="116" width="54" height="30" rx="2" fill="#1c2733" stroke="#6f8fb0"/><text x="131" y="135" text-anchor="middle" fill="#adb5bd" font-size="10">die</text><text x="70" y="135" text-anchor="middle" fill="#8b949e" font-size="8.5">mold</text><text x="192" y="135" text-anchor="middle" fill="#8b949e" font-size="8.5">mold</text><!-- RDL band --><rect x="38" y="146" width="186" height="18" rx="2" fill="#1c1430" stroke="#6b5fb0"/><g stroke="#b8732e" stroke-width="1"><line x1="118" y1="147" x2="52" y2="163"/><line x1="122" y1="147" x2="74" y2="163"/><line x1="126" y1="147" x2="96" y2="163"/><line x1="131" y1="147" x2="118" y2="163"/><line x1="131" y1="147" x2="140" y2="163"/><line x1="136" y1="147" x2="162" y2="163"/><line x1="140" y1="147" x2="184" y2="163"/><line x1="144" y1="147" x2="206" y2="163"/></g><text x="131" y="159" text-anchor="middle" fill="#c4b5fd" font-size="8">RDL — Cu in polymer</text><!-- solder balls --><g fill="#e0b13a"><circle cx="52" cy="169" r="3"/><circle cx="74" cy="169" r="3"/><circle cx="96" cy="169" r="3"/><circle cx="118" cy="169" r="3"/><circle cx="140" cy="169" r="3"/><circle cx="162" cy="169" r="3"/><circle cx="184" cy="169" r="3"/><circle cx="206" cy="169" r="3"/></g><!-- die-edge markers --><line x1="104" y1="146" x2="104" y2="178" stroke="#586069" stroke-width="0.8" stroke-dasharray="3 2"/><line x1="158" y1="146" x2="158" y2="178" stroke="#586069" stroke-width="0.8" stroke-dasharray="3 2"/><text x="70" y="187" text-anchor="middle" fill="#34d399" font-size="8.5">fan-out</text><text x="192" y="187" text-anchor="middle" fill="#34d399" font-size="8.5">fan-out</text><text x="36" y="214" fill="#adb5bd" font-size="11">A die is re-molded into a wafer.</text><text x="36" y="229" fill="#adb5bd" font-size="11">Copper RDL is built on its face and</text><text x="36" y="244" fill="#adb5bd" font-size="11">fans I/O out past the die edge.</text><text x="36" y="269" fill="#38bdf8" font-size="11" font-weight="700">No package substrate at all —</text><text x="36" y="284" fill="#38bdf8" font-size="11" font-weight="700">RDL replaces it entirely.</text><text x="36" y="309" fill="#8b949e" font-size="10.5">Package height can drop below</text><text x="36" y="323" fill="#8b949e" font-size="10.5">0.5 mm — great for mobile SoCs.</text><!-- ===== PANEL 2 ===== --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="283" y="92" fill="#38bdf8" font-size="14" font-weight="700">2 · Chip-first vs chip-last</text><text x="283" y="112" fill="#f0d9b5" font-size="11.5" font-weight="700">Chip-first (RDL last)</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="290" cy="128" r="6.5" fill="#e0b13a"/><text x="290" y="131" text-anchor="middle">1</text><circle cx="290" cy="146" r="6.5" fill="#e0b13a"/><text x="290" y="149" text-anchor="middle">2</text><circle cx="290" cy="164" r="6.5" fill="#e0b13a"/><text x="290" y="167" text-anchor="middle">3</text><circle cx="290" cy="182" r="6.5" fill="#e0b13a"/><text x="290" y="185" text-anchor="middle">4</text></g><text x="302" y="131" fill="#c9d1d9" font-size="9.7">Place dies on a carrier</text><text x="302" y="149" fill="#c9d1d9" font-size="9.7">Mold — reconstituted wafer</text><text x="302" y="167" fill="#c9d1d9" font-size="9.7">Debond the carrier</text><text x="302" y="185" fill="#c9d1d9" font-size="9.7">Build RDL on die face + balls</text><text x="283" y="203" fill="#e0913a" font-size="9.5">Simple RDL — but dies shift in the mold</text><line x1="283" y1="212" x2="477" y2="212" stroke="#30363d"/><text x="283" y="230" fill="#7ee6c0" font-size="11.5" font-weight="700">Chip-last (RDL first)</text><g font-size="9.5" font-weight="700" fill="#0d1117"><circle cx="290" cy="246" r="6.5" fill="#34d399"/><text x="290" y="249" text-anchor="middle">1</text><circle cx="290" cy="264" r="6.5" fill="#34d399"/><text x="290" y="267" text-anchor="middle">2</text><circle cx="290" cy="282" r="6.5" fill="#34d399"/><text x="290" y="285" text-anchor="middle">3</text><circle cx="290" cy="300" r="6.5" fill="#34d399"/><text x="290" y="303" text-anchor="middle">4</text></g><text x="302" y="249" fill="#c9d1d9" font-size="9.7">Build RDL on a carrier first</text><text x="302" y="267" fill="#c9d1d9" font-size="9.7">Attach known-good dies</text><text x="302" y="285" fill="#c9d1d9" font-size="9.7">Mold, then debond</text><text x="302" y="303" fill="#c9d1d9" font-size="9.7">Drop balls + singulate</text><text x="283" y="321" fill="#7ee6c0" font-size="9.5">RDL proven first — less die-shift</text><text x="283" y="343" fill="#8b949e" font-size="10">Both skip the substrate; order trades</text><text x="283" y="356" fill="#8b949e" font-size="10">yield against process steps.</text><!-- ===== PANEL 3 ===== --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="530" y="92" fill="#38bdf8" font-size="14" font-weight="700">3 · Why it wins &amp; hard parts</text><text x="530" y="112" fill="#34d399" font-size="11.5" font-weight="700">Why it wins</text><g fill="#34d399"><circle cx="534" cy="125" r="2.6"/><circle cx="534" cy="140" r="2.6"/><circle cx="534" cy="155" r="2.6"/><circle cx="534" cy="170" r="2.6"/><circle cx="534" cy="185" r="2.6"/></g><text x="544" y="128" fill="#c9d1d9" font-size="10.5">No substrate → package &lt; 0.5 mm</text><text x="544" y="143" fill="#c9d1d9" font-size="10.5">Cheaper — ~50–70% vs substrate</text><text x="544" y="158" fill="#c9d1d9" font-size="10.5">Short RDL → better electrical</text><text x="544" y="173" fill="#c9d1d9" font-size="10.5">Die near board → better thermal</text><text x="544" y="188" fill="#c9d1d9" font-size="10.5">Scales: InFO-PoP, InFO-L</text><line x1="530" y1="200" x2="724" y2="200" stroke="#30363d"/><text x="530" y="220" fill="#e0b13a" font-size="11.5" font-weight="700">The hard parts</text><g fill="#e0b13a"><circle cx="534" cy="233" r="2.6"/><circle cx="534" cy="248" r="2.6"/><circle cx="534" cy="263" r="2.6"/><circle cx="534" cy="278" r="2.6"/></g><text x="544" y="236" fill="#adb5bd" font-size="10.5">die-shift &amp; placement accuracy</text><text x="544" y="251" fill="#adb5bd" font-size="10.5">reconstituted-wafer warpage</text><text x="544" y="266" fill="#adb5bd" font-size="10.5">RDL yield over a large area</text><text x="544" y="281" fill="#adb5bd" font-size="10.5">thermal for high-power devices</text><text x="530" y="307" fill="#f87171" font-size="10.5" font-weight="700">Warpage and die movement in the</text><text x="530" y="321" fill="#f87171" font-size="10.5" font-weight="700">mold are the yield gate.</text><!-- ===== BOTTOM CARDS ===== --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="36" y="406" fill="#38bdf8" font-size="12.5" font-weight="700">No substrate, RDL on the die</text><text x="36" y="424" fill="#adb5bd" font-size="10">Copper redistribution is built straight</text><text x="36" y="437" fill="#adb5bd" font-size="10">onto the molded die face; the organic</text><text x="36" y="450" fill="#adb5bd" font-size="10">package substrate disappears.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="283" y="406" fill="#34d399" font-size="12.5" font-weight="700">Fan-out adds I/O room</text><text x="283" y="424" fill="#adb5bd" font-size="10">Routing past the die edge gives more</text><text x="283" y="437" fill="#adb5bd" font-size="10">balls at board-friendly pitch than</text><text x="283" y="450" fill="#adb5bd" font-size="10">fan-in WLCSP can.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="530" y="406" fill="#e0b13a" font-size="12.5" font-weight="700">Warpage &amp; die-shift bite</text><text x="530" y="424" fill="#adb5bd" font-size="10">Reconstituted-wafer warpage and die</text><text x="530" y="437" fill="#adb5bd" font-size="10">movement in the mold gate FOWLP</text><text x="530" y="450" fill="#adb5bd" font-size="10">yield.</text></svg>

Fan-Out Wafer-Level Packaging Process is a revolutionary packaging technology placing bare dies directly on redistribution layers without interposer substrates, enabling fan-out routing and wafer-scale integration — eliminating intermediate packaging substrates and reducing cost-per-unit.

FOWLP Architecture Overview

Fan-out packaging reorganizes die arrangement in wafer format: multiple dies bonded sparsely across wafer surface (spacing between dies enables RDL routing underneath), followed by RDL deposition creating electrical routing. Finished package contains dozens of dies per wafer; wafer-level sawn into individual package units. Cost advantage significant: substrate cost (~$5-20 per unit in traditional packages) eliminated, replaced by thin RDL ($0.50-2 per unit); net savings 50-70% depending on package complexity. Density improvement: dies no longer constrained by package body outline, enabling arbitrary spatial arrangement.

Chip-First vs Chip-Last Process Flows

Chip-first sequence: dies bonded to temporary carrier substrate, micro-bumps formed on die pads, RDL subsequently deposited/routed, interconnect completed, dies singulated from temporary carrier. Advantages: rework capability (defective dies can be removed before RDL complete), simpler RDL patterning (no die obstruction). Disadvantages: temporary carrier removal adds process complexity, potential damage during carrier peel-off.

Chip-last sequence: RDL fabricated on temporary substrate first (all metal layers, vias, and pads complete), dies subsequently bonded to RDL pads (micro-bump bonding or solder-reflow with flux), underfill applied, singulation follows. Advantages: tighter RDL pitch (no die presence constrains patterning), simplified assembly. Disadvantages: no die rework capability (defective dies cannot be removed), RDL lithography complexity managing registration around future die bonding pads.

Temporary Carrier Technology

• Carrier Materials: Silicon or glass wafers serve as temporary mechanical support; alternative polymeric carriers reduce processing cost
• Release Mechanisms: Thermal release polymers (TRP) with temperature-dependent adhesion enable carrier removal at elevated temperature without mechanical stress
• Adhesion Control: Careful process parameter tuning controls adhesion strength — sufficient to prevent die slippage during processing, but enabling clean separation afterward
• Reuse Strategy: Carriers cleaned and reused 50-100 times improving process economics

Underfill Material and Encapsulation

• Epoxy Systems: Thermosetting epoxy underfill provides mechanical stability through thermal cross-linking (cure at 150-180°C)
• Curing Chemistry: Aliphatic or cycloaliphatic epoxy resins cured with anhydride or amine hardeners; cure kinetics optimized for processing speed
• Coefficient of Thermal Expansion (CTE): Underfill CTE matched to silicon (approximately 3 ppm/K) minimizing stress during thermal cycling
• Hydrophobicity: Hydrophobic resins resist moisture ingress protecting internal structures

RDL Integration in FOWLP

• Multi-Layer RDL: Typically 3-4 metal layers with 2-5 μm pitch enable complex routing patterns under sparse die placement
• Via-Rich Areas: High via density (20-40% area) under dies provides electrical distribution from die bumps to RDL routing network
• Routing Layers: Upper metal layers route signals across wafer enabling arbitrary die-to-die connection patterns
• Power Distribution: Dedicated power/ground layers carry high current from substrate pads to all dies

Reconstituted Wafer Processing

After die bonding and underfill cure, assembly treated as standard wafer enabling back-end-of-line processing: backside substrate removal (if used), additional RDL layers, and final substrate pads. This wafer-level processing provides efficiency advantage — tool utilization matches standard wafer manufacturing (no per-unit assembly, handled at wafer scale). Finishing requires wafer singulation through saw or laser scribing separating packages.

Embedded Wafer-Level BGA (eWLB)

eWLB variant embeds dies within molded compound — dies bonded to temporary carrier, RDL deposited, subsequently encapsulated in mold compound creating solid package body. Mold compound provides mechanical robustness and hermetic-equivalent protection (moisture resistance adequate for most non-military applications). Backside solder balls attached through solder-mask patterning and ball attachment completing package. eWLB combines fan-out benefits with traditional ball-grid-array form factor enabling direct PCB assembly without specialized equipment.

Design Considerations and Constraints

• Die Pitch Optimization: Sparse die placement enables cost-effective RDL routing; typical inter-die spacing 2-5 mm balances routing flexibility against wafer area utilization
• Power Delivery Network: Multiple dies sharing power/ground infrastructure require careful voltage drop analysis ensuring <50 mV drop across wafer under worst-case current transients
• Thermal Management: Dies dissipating significant power require direct thermal connection to substrate — alternative thermal vias (large-diameter high-conductivity paths) route heat away from sensitive circuits
• Signal Integrity: Long RDL traces introduce parasitic inductance and capacitance; differential routing pairs and controlled impedance essential for high-speed signals

Yield and Reliability

• Process Yield: Defect probability increases with RDL complexity; layer-by-layer yield (95%+ per layer) cumulative across 3-4 layers results in 85-95% RDL yield
• Thermal Cycling Reliability: CTE mismatch between underfill (≈50 ppm/K), silicon dies (3 ppm/K), and solder interconnect (20 ppm/K) creates thermal stress; reliability assessed through -40°C to +85°C cycling
• Moisture Absorption: Polymer underfill absorbs moisture (2-5% water content after humidity conditioning) causing expansion; moisture-induced stresses critical failure mechanism

Closing Summary

Fan-out wafer-level packaging represents a paradigm-shifting technology enabling direct die-to-RDL bonding at wafer scale, eliminating expensive interposer substrates while enabling dense heterogeneous integration — transforming packaging economics and enabling next-generation multi-chiplet systems through wafer-scale manufacturing efficiency.