Fuse, Antifuse, and OTP (One-Time Programmable) Memory are the non-volatile storage elements integrated into CMOS chips that can be permanently programmed once after manufacturing — used for chip ID, security keys, memory repair addresses, analog trimming values, and configuration data, where the permanent and irreversible nature of programming provides both tamper resistance and the ability to customize each chip individually during test and packaging.

Types of OTP Elements

eFuse (Most Common in Modern CMOS)

<svg viewBox="0 0 510 131" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="510" height="131" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Unprogrammed:  [Anode]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Silicided Poly Link]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Cathode]</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">               Low resistance (~100-200 Ω)</tspan></text><text xml:space="preserve" x="20" y="69.7"></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9">Programmed:    [Anode]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[  Broken Link  ]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Cathode]</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#c9d1d9">               High resistance (&gt;10 kΩ)</tspan></text></g></svg>

• Programming: Apply ~1.2V × 10mA for 10-100 µs → current melts silicide → poly link opens.
• Read: Sense resistance → low = '0' (intact), high = '1' (blown).
• Size: ~1-2 µm² per bit in advanced CMOS.
• Reliability: Resistance ratio >100:1 → robust read margin.

Antifuse

<svg viewBox="0 0 477 131" xmlns="http://www.w3.org/2000/svg" style="max-width:100%;height:auto" role="img"><rect x="0" y="0" width="477" height="131" rx="12" fill="#0d1117"/><g font-family="ui-monospace,SFMono-Regular,Menlo,Consolas,&quot;Liberation Mono&quot;,monospace" font-size="14"><text xml:space="preserve" x="20" y="31.7"><tspan fill="#c9d1d9">Unprogrammed:  [Metal 1]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Thin Oxide]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Metal 2]</tspan></text><text xml:space="preserve" x="20" y="50.7"><tspan fill="#c9d1d9">               High resistance (&gt;1 GΩ, oxide intact)</tspan></text><text xml:space="preserve" x="20" y="69.7"></text><text xml:space="preserve" x="20" y="88.7"><tspan fill="#c9d1d9">Programmed:    [Metal 1]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Breakdown]</tspan><tspan fill="#6e7681">──</tspan><tspan fill="#c9d1d9">[Metal 2]</tspan></text><text xml:space="preserve" x="20" y="107.7"><tspan fill="#c9d1d9">               Low resistance (&lt;1 kΩ, oxide broken)</tspan></text></g></svg>

• Programming: Apply 5-8V across thin oxide → dielectric breakdown → conductive path forms.
• Opposite of fuse: Starts open, becomes closed after programming.
• Advantage: Very small area (~0.1 µm² per bit), high density.
• Used in: FPGA routing (antifuse-based FPGAs), security keys.

Applications

Memory Repair Flow

1. Test: MBIST identifies failing SRAM rows/columns. 2. Analyze: Repair algorithm selects optimal redundant row/column assignments. 3. Program: Blow eFuses encoding repair addresses. 4. Verify: Re-read fuses → confirm correct programming. 5. Retest: Run MBIST again → failing cells now redirected to redundant cells → chip passes.

Security Considerations

• eFuse: Physically visible under SEM → can be reverse-engineered.
• Antifuse: Oxide breakdown not easily visible → better for security.
• Both: One-time only → cannot be overwritten → tamper evidence.
• Key storage: Program AES/RSA keys → chip boots only with correct key → secure boot.

Comparison with Flash OTP

Fuse and antifuse OTP elements are the permanent personalization technology that transforms identical silicon dice into individually configured products — from storing repair addresses that rescue otherwise failing memories to holding the cryptographic keys that anchor hardware security, OTP elements provide the non-volatile, tamper-resistant, zero-additional-mask-cost storage that every modern chip requires for post-fabrication customization.