Gate-All-Around (GAA) Nanosheet Transistor Process is the next-generation CMOS architecture succeeding FinFET where the gate electrode completely wraps around multiple horizontally-stacked silicon nanosheet channels — providing superior electrostatic control over the channel from all four sides versus FinFET's three-sided gate, enabling continued voltage scaling, reduced leakage, and greater design flexibility through adjustable sheet width, first deployed in Samsung's 3nm GAA and planned for TSMC's N2 and Intel's 18A nodes.
Why GAA Replaces FinFET
FinFET's vertical fin has the gate wrapped on three sides (top and two sidewalls), with the bottom of the fin connected to the substrate (ungated). At sub-3nm nodes, the fin becomes too narrow (<5nm) for reliable process control, and the ungated bottom surface degrades short-channel effects. GAA eliminates this: the gate surrounds the channel entirely, providing the best possible electrostatic control: SS (subthreshold swing) approaching the 60 mV/decade theoretical limit.
Nanosheet Formation Process
1. Superlattice Epitaxy: Alternate layers of Si and SiGe are epitaxially grown on the wafer — typically 3-4 pairs. Each Si layer becomes a channel nanosheet (~5-7nm thick); each SiGe layer is a sacrificial spacer (~8-12nm thick).
2. Fin Patterning: The superlattice stack is etched into fin-like structures using the same patterning approach as FinFET.
3. Dummy Gate and Spacer Formation: A sacrificial polysilicon gate is formed. Inner spacers are created by selectively recessing the SiGe layers from the source/drain side and backfilling with dielectric — these inner spacers insulate the gate from the source/drain.
4. Source/Drain Epitaxy: Epitaxial Si:P (NMOS) or SiGe:B (PMOS) is grown on the exposed nanosheet edges, forming the source and drain contacts.
5. Dummy Gate Removal: The sacrificial poly gate is etched away, exposing the nanosheet stack in the channel region.
6. Channel Release: The critical step — SiGe is selectively etched away using vapor-phase HCl or wet chemistry, leaving freestanding Si nanosheets suspended in the gate cavity. Selectivity >100:1 (SiGe:Si) is required.
7. High-k/Metal Gate: ALD deposits HfO₂ (high-k) and work-function metals (TiN, TiAl, TaN) conformally around all surfaces of each nanosheet. The gate completely surrounds every channel.
Design Flexibility
Unlike FinFETs (where drive current is quantized by fin count — 1 fin, 2 fins, 3 fins), nanosheet width is continuously adjustable. Wider nanosheets deliver more current; narrower ones save area. This enables finer granularity in power-performance trade-offs within the same technology.
Process Challenges
- Channel Release Selectivity: Removing SiGe without attacking Si channels or the surrounding structures requires atomic-level selectivity.
- Gate Fill in Tight Spaces: The gap between nanosheets (~8-12nm) must be filled with multiple atomic layers of dielectric and metal — a few nm of space for work-function metal.
- Variability: Nanosheet thickness uniformity (±0.5nm across wafer) directly affects threshold voltage.
GAA Nanosheet is the transistor architecture that achieves the theoretical ideal of complete gate control — wrapping the gate electrode around the channel from every direction, extracting the last drops of scaling benefit from silicon before physics demands entirely new channel materials.