GAA (Gate-All-Around) Process Integration is the full transistor fabrication sequence for nanosheet or nanowire gate-all-around FETs, where the gate electrode wraps completely around the channel on all four sides — the transistor architecture adopted starting at 3nm (Samsung) and 2nm (TSMC, Intel) to overcome the electrostatic limitations of FinFET that emerge below 5nm. GAA integration introduces fundamentally new process modules (superlattice epitaxy, channel release, inner spacer formation) while retaining many FinFET process elements.

GAA vs. FinFET Structure

FinFET cross-section:        GAA Nanosheet cross-section:
    ┌────────┐                   ┌────────┐
    │  Gate  │                   │  Gate  │
    └──┬─┬──┘              ┌─────┴────────┴─────┐
      │ │                  │  NS3 (channel)      │
      │ Fin │              │     Gate (wrap)      │
      │ │                  │  NS2 (channel)      │
    ──┴─┴──                │     Gate (wrap)      │
    Substrate               │  NS1 (channel)      │
                            └──────────────────────┘

Key Advantage: Gate wraps around each nanosheet → superior electrostatic control → lower IOFF, better subthreshold slope → enables shorter gate lengths at same leakage.

GAA Process Flow (Key New Modules)

Step 1: Superlattice Epitaxy

• Grow alternating Si / SiGe layers (superlattice) on substrate.
• Typical stack: 3–5 pairs of Si (4–6 nm thick) / SiGe₃₀ (8–12 nm thick).
• Si → becomes nanosheet channels; SiGe₃₀ → sacrificial layers (later removed).
• Requires precise thickness control: ±0.5 nm per layer.

Step 2: Fin Patterning

• EUV or multi-patterned DUV lithography patterns superlattice into fin shapes.
• Fin etch stops on substrate — entire superlattice stack now forms a multi-layer fin.

Step 3: Dummy Gate + Spacer Formation

• Poly dummy gate deposited and patterned across fins.
• Outer spacer (SiO₂ or SiOCN) deposited on dummy gate sidewalls.

Step 4: SiGe Recess + Inner Spacer Formation ← Key new step

• Selective lateral etch of SiGe sacrificial layers through S/D opening.
• Creates cavities between Si nanosheets laterally (under outer spacer region).
• ALD-fill with low-k dielectric (SiOCN) → etch-back → forms inner spacers in cavities.
• Inner spacer function: Electrically isolates gate metal from S/D → reduces parasitic capacitance.

Step 5: S/D Epitaxy

• Epitaxially grow S/D: Si:P (NMOS) or SiGe:B (PMOS) anchored to all exposed Si nanosheet ends.
• Merging epi fills space between nanosheets → provides current path.

Step 6: ILD + CMP

• Interlayer dielectric deposited → CMP stops on dummy gate cap.

Step 7: Dummy Gate Removal + Channel Release ← Most critical new step

• Poly dummy gate etched selectively.
• SiGe sacrificial layers etched selectively vs. Si (using HCl vapor or wet SiGe-selective etch).
• Si nanosheets now suspended, connected only at S/D ends → sheets are free-standing.

Step 8: High-k + Metal Gate Fill

• ALD high-k (HfO₂) deposited conformally around all four sides of each nanosheet.
• Work function metal (TiN, TaN, Al-doped metals) fill gaps between nanosheets → must completely fill narrow inter-nanosheet gaps (<5 nm).
• W or Ru metal fill for low resistance.

Step 9: Gate CMP + MOL/BEOL

• Standard backend continues as in FinFET process.

GAA Integration Challenges

GAA nanosheet process integration is the defining manufacturing challenge of the 2nm era — each new process module (superlattice epitaxy, channel release, inner spacer) requires years of optimization, but the resulting improvement in electrostatic control and density over FinFET justifies the complexity and cost for leading-edge logic manufacturing.