For two decades, the transistor got faster mainly by getting smaller and taller. The FinFET — a vertical silicon fin with the gate draped over three sides — carried the industry from 22nm down to 3nm. At 2nm-class nodes that geometry runs out of room: the fin is too thin to control reliably and leakage climbs. Gate-all-around (GAA) is the successor structure, and it is the single change that defines the leading edge every advanced-AI chip is now designed into.\n\nWhy the transistor had to change. A transistor is a switch; the gate turns the channel on and off. The more sides of the channel the gate touches, the more completely it controls the flow of current and the less the transistor leaks when it is supposed to be off. FinFET gates a fin on three sides. As nodes shrank, the fin got so narrow that adding more of them was the only way to raise drive current, and off-state leakage became the dominant power tax. The physics stopped cooperating.\n\nWhat "gate-all-around" actually means. GAA lays the channel down as a set of horizontal silicon sheets — nanosheets — and wraps the gate material completely around each one, all four sides. That full electrostatic wrap gives near-ideal control: sharper on/off switching, lower leakage, and the ability to run at lower voltage. Because the sheets are stacked, a designer adds drive current by stacking more sheets rather than widening the footprint, and can tune sheet width per circuit to trade speed against power. Intel markets its version as RibbonFET; Samsung calls its flavor MBCFET; the underlying idea is the same.\n\n| Node | Vendor | Transistor | Backside power | Status |\n|---|---|---|---|---|\n| N2 | TSMC | GAA nanosheet | No (frontside) | High-volume ramp, late 2025 into 2026 |\n| 18A | Intel | RibbonFET GAA | Yes (PowerVia) | Ramp to mass production, 2025-2026 |\n| SF2 | Samsung | MBCFET GAA | No (frontside) | In production, yield still maturing |\n\n``svg\n\n``\n\nWhy GAA is the gate that decides the AI node. Every 2nm-class part — the logic dies inside next-generation GPUs, accelerators, and the CPUs that host them — is a GAA design. Relative to a mature 3nm node, TSMC positions N2 at roughly 10 to 15 percent more performance at the same power, or about 25 to 30 percent less power at the same performance, with a meaningful density gain. Those numbers compound directly into tokens-per-watt for inference and training-throughput-per-rack, which is why access to a working GAA node is now a competitive dividing line rather than a routine process step.\n\nThe three-way race. Three companies are bringing GAA to volume at once. TSMC's N2 is the highest-volume path and keeps power delivery on the front of the wafer, saving its backside-power option for later N2 derivatives and the A16 generation. Intel's 18A pairs RibbonFET with PowerVia backside power delivery in the same node — a more aggressive bundling that, if yields hold, leapfrogs on power delivery. Samsung reached GAA first with its 3nm MBCFET and is pushing SF2, though its challenge has been yield and customer commitment rather than the transistor concept. For the first time in years the leading-edge roadmap is genuinely contested, and the transistor architecture is the reason.\n\nRead through a quant lens rather than a device-physics lens, and GAA node readiness is the gating variable for who can build competitive AI silicon in 2026 and beyond — a supplier's ability to yield a 2nm-class GAA process is the leading indicator for whether its customers' next accelerators are performance-competitive at all. How nanosheet width tuning maps to library-level PPA, why backside power (PowerVia, Super Power Rail) is the natural companion to GAA, and how CFET — stacking n and p devices vertically — extends the idea past 2nm are the natural next layers to go deeper on.