Gate-All-Around (GAA) FET is the next-generation transistor architecture succeeding FinFET, where the gate completely surrounds horizontal nanosheet or nanowire channels for maximum electrostatic control. Structure: multiple stacked horizontal silicon channels (nanosheets, typically 3-4 stacks) with gate material wrapping all four sides of each channel. Key dimensions: sheet width (variable, 15-50nm for drive strength tuning), sheet thickness (5-7nm), sheet spacing (10-12nm), gate length (12-14nm at initial nodes). Advantages over FinFET: (1) Variable width—sheet width is continuous (vs. FinFET quantized fin count); (2) Better electrostatics—gate on all four sides vs. three; (3) Higher drive current per footprint—wider effective channel width; (4) Improved short-channel control—better DIBL and subthreshold slope. Fabrication: (1) Grow Si/SiGe superlattice epitaxially; (2) Pattern fins using SAQP; (3) Form dummy gate; (4) Release channels by selectively etching SiGe (inner spacer formation); (5) Deposit high-κ/metal gate around channels. Manufacturing challenges: inner spacer formation, uniform channel release, conformal gate deposition in tight spaces, work function metal tuning for NMOS/PMOS. Industry adoption: Samsung 3nm GAA (MBCFET, 2022), TSMC N2 (nanosheet, 2025), Intel 20A (RibbonFET, 2024). Future: forksheet FET (shared gate wall between NMOS/PMOS) and CFET (complementary FET with NMOS stacked on PMOS) for further density scaling.