Gate-All-Around (GAA) Nanosheet Transistor Technology is the next-generation transistor architecture where the gate electrode completely surrounds horizontally stacked silicon nanosheet channels on all four sides — providing superior electrostatic control over FinFETs and enabling continued transistor scaling at 3 nm and below with adjustable channel width for optimized power-performance trade-offs.
Nanosheet Architecture:
- Stacked Channel Structure: 3-4 horizontally stacked silicon nanosheets (typical thickness 5-7 nm, width 10-50 nm) suspended between source and drain; gate dielectric and metal gate fill the spaces between and around each sheet
- Width Flexibility: unlike FinFETs with quantized fin-based width, nanosheet width is continuously adjustable by lithographic patterning; enables fine-grained optimization of drive current for different circuit blocks (logic, SRAM, analog)
- Effective Width: total drive current proportional to 2×(sheet width + sheet thickness) × number of sheets; wider nanosheets deliver more current per footprint than equivalent multi-fin FinFETs
- Nomenclature: Samsung calls them multi-bridge channel FET (MBCFET); Intel refers to RibbonFET; TSMC uses nanosheet terminology; all describe the same fundamental GAA horizontal nanosheet concept
Fabrication Process:
- Superlattice Epitaxy: alternating Si/SiGe layers (typically 8-10 layers total) grown epitaxially on silicon substrate; SiGe layers serve as sacrificial spacers; Si layers become the nanosheet channels after SiGe removal
- Channel Release: highly selective isotropic etch removes SiGe sacrificial layers while preserving Si nanosheets; selectivity >100:1 (SiGe:Si) required; vapor-phase HCl or wet chemical etch used; critical step defining channel quality
- Inner Spacer Formation: after SiGe recess, dielectric inner spacers deposited and etched back between nanosheet layers; inner spacers isolate gate from source/drain and control parasitic capacitance; SiN or SiCO materials with k < 5
- Gate Fill: conformal ALD deposition of high-k dielectric and work function metals must uniformly coat all nanosheet surfaces including narrow gaps (8-12 nm) between sheets; void-free fill is critical for device performance and reliability
Performance Advantages Over FinFET:
- Electrostatic Control: gate surrounding channel on all four sides provides near-ideal subthreshold swing (~62 mV/decade) and DIBL <30 mV/V; superior short-channel effect immunity at gate lengths below 12 nm
- Drive Current: wider nanosheets deliver 15-30% higher drive current per unit footprint compared to FinFETs at equivalent leakage; enables either higher performance or smaller cell area
- Power Efficiency: improved SS and DIBL allow lower operating voltage (Vdd) for same performance; 5-10% Vdd reduction translates to 10-20% dynamic power savings at iso-performance
- Vt Tuning: work function metal thickness modulation between nanosheet layers enables precise threshold voltage control; 4-5 Vt flavors achievable through dipole and metal gate engineering
Challenges and Solutions:
- Thermal Budget: nanosheet release and gate stack formation require careful thermal management to prevent Si/SiGe intermixing; maximum process temperature limited after superlattice growth
- Parasitic Resistance: source/drain epitaxy must make low-resistance contact to edges of each nanosheet layer; wrap-around epitaxial growth and high-doping concentration (>2×10²¹ cm⁻³) minimize access resistance
- Reliability: gate dielectric integrity in confined spaces between nanosheets; bias temperature instability (BTI) and hot carrier injection (HCI) must meet 10-year lifetime requirements; inner spacer quality affects TDDB performance
- Stacking Density: increasing from 3 to 4+ nanosheet layers improves drive current but increases process complexity and vertical stack height; CFET (complementary FET) stacks NMOS nanosheets above PMOS for ultimate density
GAA nanosheet transistors are the definitive successor to FinFETs — their four-sided gate control and flexible channel width unlock the next era of semiconductor scaling, enabling 3 nm and 2 nm technology nodes that power the most advanced AI chips, mobile processors, and high-performance computing systems.