<svg viewBox="0 0 760 470" xmlns="http://www.w3.org/2000/svg" font-family="-apple-system,Segoe UI,Roboto,Helvetica,Arial,sans-serif"><rect x="0" y="0" width="760" height="470" rx="14" fill="#0d1117"/><text x="20" y="30" fill="#e6edf3" font-size="19" font-weight="700">Nanowire FET: wrap the gate all the way around the channel</text><text x="20" y="50" fill="#8b949e" font-size="12.5">Gate-all-around gives the best electrostatics &#8212; stack the wires back to get the drive current</text><!-- Panel 1 --><rect x="20" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="32" y="88" fill="#7ee6c0" font-size="13" font-weight="700">1 &#183; More gated sides</text><text x="32" y="106" fill="#8b949e" font-size="10.5">how much of the channel the gate touches</text><!-- planar --><rect x="42" y="150" width="44" height="16" rx="1" fill="#38506a"/><rect x="42" y="140" width="44" height="10" rx="1" fill="#d08a4a"/><text x="64" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">planar</text><text x="64" y="194" fill="#8b949e" font-size="8" text-anchor="middle">1 side</text><!-- finfet --><rect x="128" y="134" width="30" height="40" rx="2" fill="#d08a4a"/><rect x="136" y="140" width="14" height="34" rx="1" fill="#38506a"/><text x="143" y="182" fill="#adb5bd" font-size="8.5" text-anchor="middle">FinFET</text><text x="143" y="194" fill="#8b949e" font-size="8" text-anchor="middle">3 sides</text><!-- gaa --><circle cx="204" cy="154" r="18" fill="#d08a4a"/><circle cx="204" cy="154" r="9" fill="#34d399"/><text x="204" y="182" fill="#7ee6c0" font-size="8.5" text-anchor="middle">GAA wire</text><text x="204" y="194" fill="#8b949e" font-size="8" text-anchor="middle">all around</text><!-- arrow of progression --><line x1="42" y1="210" x2="222" y2="210" stroke="#3f9d6f" stroke-width="1.2" marker-end="url(#nw)"/><text x="132" y="224" fill="#34d399" font-size="8.5" text-anchor="middle">tighter electrostatic control</text><text x="32" y="248" fill="#adb5bd" font-size="9.5">Wrapping the gate on every side lets</text><text x="32" y="263" fill="#adb5bd" font-size="9.5">it shut the channel completely: a</text><text x="32" y="278" fill="#adb5bd" font-size="9.5">steeper subthreshold slope and far</text><text x="32" y="293" fill="#adb5bd" font-size="9.5">less drain-induced leakage than a fin.</text><text x="32" y="316" fill="#8b949e" font-size="9.5">Copper = gate &#183; green = silicon channel.</text><text x="32" y="338" fill="#8b949e" font-size="9.5">This is the device behind the &#8220;GAA&#8221;</text><text x="32" y="353" fill="#8b949e" font-size="9.5">nanosheet node at 2nm-class logic.</text><!-- Panel 2 --><rect x="267" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="279" y="88" fill="#9fd8ef" font-size="13" font-weight="700">2 &#183; One wire is too thin</text><text x="279" y="106" fill="#8b949e" font-size="10.5">stack channels to add drive width</text><!-- single wire --><text x="322" y="130" fill="#adb5bd" font-size="9" text-anchor="middle">single wire</text><circle cx="322" cy="170" r="20" fill="#d08a4a"/><circle cx="322" cy="170" r="10" fill="#34d399"/><text x="322" y="204" fill="#8b949e" font-size="8" text-anchor="middle">low current</text><!-- stacked --><text x="426" y="130" fill="#7ee6c0" font-size="9" text-anchor="middle">stacked sheets</text><rect x="404" y="140" width="44" height="72" rx="8" fill="#d08a4a"/><rect x="412" y="150" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="171" width="28" height="10" rx="4" fill="#34d399"/><rect x="412" y="192" width="28" height="10" rx="4" fill="#34d399"/><text x="426" y="224" fill="#7ee6c0" font-size="8" text-anchor="middle">3&#215; the width</text><line x1="352" y1="170" x2="398" y2="170" stroke="#8b949e" stroke-width="1" marker-end="url(#nw2)"/><text x="279" y="250" fill="#adb5bd" font-size="9.5">A lone nanowire has a tiny perimeter,</text><text x="279" y="265" fill="#adb5bd" font-size="9.5">so it carries little current. Stacking</text><text x="279" y="280" fill="#adb5bd" font-size="9.5">several sheets under one shared gate</text><text x="279" y="295" fill="#adb5bd" font-size="9.5">multiplies effective width in the same</text><text x="279" y="310" fill="#adb5bd" font-size="9.5">footprint &#8212; this is the nanosheet FET.</text><text x="279" y="333" fill="#8b949e" font-size="9.5">Sheet width is tunable: wide for drive,</text><text x="279" y="348" fill="#8b949e" font-size="9.5">narrow for low-power cells.</text><!-- Panel 3 --><rect x="514" y="66" width="226" height="298" rx="7" fill="#0c141d" stroke="#30363d"/><text x="526" y="88" fill="#c4b5fd" font-size="13" font-weight="700">3 &#183; How it&#8217;s built</text><text x="526" y="106" fill="#8b949e" font-size="10.5">the Si / SiGe superlattice trick</text><circle cx="532" cy="126" r="2.4" fill="#9fd8ef"/><text x="542" y="129" fill="#e6edf3" font-size="10" font-weight="700">Grow a superlattice</text><text x="542" y="143" fill="#8b949e" font-size="9">alternating Si and SiGe epitaxial</text><text x="542" y="156" fill="#8b949e" font-size="9">layers &#8212; Si becomes the channels.</text><circle cx="532" cy="176" r="2.4" fill="#34d399"/><text x="542" y="179" fill="#e6edf3" font-size="10" font-weight="700">Release the channels</text><text x="542" y="193" fill="#8b949e" font-size="9">a selective etch removes the SiGe,</text><text x="542" y="206" fill="#8b949e" font-size="9">leaving suspended Si wires/sheets.</text><circle cx="532" cy="226" r="2.4" fill="#e0b13a"/><text x="542" y="229" fill="#e6edf3" font-size="10" font-weight="700">Wrap gate + inner spacer</text><text x="542" y="243" fill="#8b949e" font-size="9">high-k/metal fills all around each</text><text x="542" y="256" fill="#8b949e" font-size="9">sheet; spacers isolate it from S/D.</text><rect x="526" y="272" width="202" height="82" rx="5" fill="#111a24" stroke="#30363d"/><text x="536" y="290" fill="#e0b13a" font-size="10" font-weight="700">Nanowire &#8594; nanosheet &#8594; CFET</text><text x="536" y="306" fill="#adb5bd" font-size="9">The wire was the lab prototype; wide</text><text x="536" y="320" fill="#adb5bd" font-size="9">sheets made it manufacturable (GAA).</text><text x="536" y="334" fill="#adb5bd" font-size="9">Next, CFET stacks nMOS over pMOS</text><text x="536" y="348" fill="#adb5bd" font-size="9">sheets to fold the cell in half.</text><!-- bottom cards --><rect x="20" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="32" y="406" fill="#34d399" font-size="11" font-weight="700">Gate-all-around</text><text x="32" y="424" fill="#adb5bd" font-size="9.5">Gate surrounds the channel on every</text><text x="32" y="440" fill="#adb5bd" font-size="9.5">side &#8212; the tightest control possible.</text><rect x="267" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="279" y="406" fill="#9fd8ef" font-size="11" font-weight="700">Drive by stacking</text><text x="279" y="424" fill="#adb5bd" font-size="9.5">More sheets = more width = more</text><text x="279" y="440" fill="#adb5bd" font-size="9.5">current, with no extra floor area.</text><rect x="514" y="384" width="226" height="70" rx="7" fill="#111a24" stroke="#30363d"/><text x="526" y="406" fill="#e0b13a" font-size="11" font-weight="700">The GAA lineage</text><text x="526" y="424" fill="#adb5bd" font-size="9.5">Nanowire &#8594; nanosheet is how logic</text><text x="526" y="440" fill="#adb5bd" font-size="9.5">moved past FinFET at 3/2nm.</text><defs><marker id="nw" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#3f9d6f"/></marker><marker id="nw2" markerWidth="7" markerHeight="7" refX="6" refY="3" orient="auto"><path d="M0 0 L6 3 L0 6 z" fill="#8b949e"/></marker></defs></svg>

Nanosheet Width Optimization is the critical design parameter in gate-all-around (GAA) transistors that controls the effective drive current, parasitic capacitance, and electrostatic behavior by setting the physical width of each silicon nanosheet channel — replacing the fin width as the primary device sizing knob. Unlike FinFETs where drive current is quantized by adding fins, GAA nanosheets allow continuous width tuning within process limits, enabling more precise performance/power optimization for each cell in a standard cell library.

Nanosheet Width as Device Sizing

• FinFET sizing: Current ∝ number of fins (integer steps) → coarse granularity (1x, 2x, 3x fin).
• Nanosheet sizing: Current ∝ nanosheet width (Wns) × number of stacked sheets → finer granularity.
• Typical width range: 8–70 nm per sheet, with minimum pitch set by lithography.
• Sheet count: 2–5 per stack (3 is most common at 3nm).

Drive Current vs. Nanosheet Width

• Ion ∝ Wns (linear) — wider sheets → more channel area → more current per stack.
• But parasitics also scale: Cgg, Cgd, junction capacitance all increase with Wns.
• Design sweet spot: Wns that maximizes Ion/Cgg (intrinsic frequency performance).

NMOS vs. PMOS Width Optimization

Width Optimization for Standard Cell Design

• Standard cells (inverter, NAND, NOR) target NMOS/PMOS current balance → different Wns for N vs. P.
• At 3nm (Samsung SF3): NMOS uses 3 × Si sheets; PMOS uses 3 × SiGe sheets with wider Wns or different Ge%.
• Separate NMOS/PMOS sheet definition enabled by CMOS GAA integration flow: grow Si/SiGe superlattice for NMOS, SiGe/Si for PMOS (or mix-and-match channels).

Electrostatics vs. Width

• Shorter sheet width → better electrostatic control (gate wraps more completely → less fringe field from S/D).
• Wider sheet → drain-induced barrier lowering (DIBL) increases slightly.
• Minimum sheet width set by short-channel control spec (DIBL < 50–100 mV/V), not just lithography.

Process Constraints on Nanosheet Width

• Maximum width: Limited by nanosheet release etch — very wide sheets sag without support → structural failure.
• Minimum width: Limited by lithography (EUV patterning minimum), contact resistance (too narrow → current crowding).
• Sheet-to-sheet variation: Epitaxial thickness variation → each sheet slightly different width → VT variation → σVT increases.

Width Tuning for Low-Power vs. High-Performance

Industry Implementations

• Samsung SF3 (3nm GAA): 3 Si nanosheets, Wns ~20–40 nm, sheet thickness 4–5 nm.
• TSMC N2 (2nm): Nanosheet GAA replacing FinFET; Wns details proprietary but similar range.
• Intel 20A/18A: RibbonFET (nanosheet variant); width tuning cited as key performance lever.

Nanosheet width optimization is the central lever for achieving performance-power targets in GAA transistor design — by providing a continuous, analog-like control over drive current and capacitance that FinFET's discrete fin count could not match, nanosheet width tuning enables circuit designers and process engineers to collaborate at a new level of precision in defining what each logic standard cell delivers at 3nm and beyond.