Gate-All-Around (GAA) Transistor is the next-generation CMOS device architecture where the gate electrode completely surrounds the channel on all sides — providing superior electrostatic control over the channel compared to FinFET, enabling continued transistor scaling to 3nm, 2nm, and beyond by suppressing short-channel effects and reducing leakage current by 2-3 orders of magnitude at equivalent gate length.
GAA Structure and Advantages:
- Complete Gate Control: gate wraps 360° around the channel (nanosheet, nanowire, or nanoribbon); effective gate width equals channel perimeter × number of stacked channels; eliminates the ungated bottom surface present in FinFETs where only three sides are gated
- Electrostatic Superiority: subthreshold swing approaches ideal 60 mV/decade even at gate lengths below 12nm; drain-induced barrier lowering (DIBL) reduced to <20 mV/V vs 40-60 mV/V for equivalent FinFET; enables 30% lower operating voltage at same leakage target
- Width Quantization Elimination: FinFET width is quantized in fin-pitch increments (~20-30nm); GAA nanosheet width is lithographically defined (5-50nm continuously variable); enables precise drive current tuning for standard cell library optimization without area penalty
- Stacked Channel Scaling: performance scales linearly with number of vertically stacked nanosheets (2-6 sheets typical); Samsung 3nm GAA uses 3 sheets, 2nm uses 4-5 sheets; each sheet contributes independently to drive current while sharing a single gate footprint
Fabrication Process Flow:
- Superlattice Formation: alternating layers of Si (channel) and SiGe (sacrificial) epitaxially grown on substrate; typical stack: 5-7nm Si / 10-12nm SiGe × 3-5 repeats; SiGe composition 25-40% Ge for etch selectivity; total stack height 80-120nm determines final transistor height
- Fin Patterning: EUV lithography (0.33 NA, 13.5nm wavelength) defines fin structures; 193nm immersion multi-patterning (SAQP - Self-Aligned Quadruple Patterning) used for 5nm/3nm nodes; fin pitch 20-30nm; critical dimension uniformity <1.5nm (3σ) required for threshold voltage matching
- Dummy Gate Formation: sacrificial poly-Si gate deposited and patterned; spacer formation (SiN, 4-6nm thick) using ALD; source/drain recess etch removes Si/SiGe stack in S/D regions; epitaxial S/D growth (SiP for NMOS at 650-700°C, SiGe:B for PMOS at 550-600°C) with in-situ doping
- SiGe Release Etch: remove dummy gate; selective isotropic etch removes SiGe layers using vapor HCl at 600-700°C or wet etch (H₂O₂:HF mixture); etch selectivity Si:SiGe >100:1 required; creates suspended Si nanosheets with 10-15nm vertical spacing
Gate Stack Integration:
- Inner Spacer Formation: critical innovation enabling GAA; low-k dielectric (SiOCN, SiCO, k~4-5) deposited conformally then anisotropically etched to remain only between nanosheet edges and S/D regions; prevents gate-to-S/D capacitance and leakage; thickness 3-5nm, length 5-8nm
- High-k Metal Gate (HKMG): conformal ALD of HfO₂ (2-3nm, EOT 0.7-0.9nm) wraps all nanosheet surfaces; work function metal (TiN, TaN, or TiAlC for NMOS; TiN for PMOS) deposited by ALD at 300-400°C; gate fill metal (W or Co) via CVD; CMP planarization
- Interface Engineering: chemical oxide (0.5-0.8nm) formed before HfO₂ deposition using ozone or plasma oxidation; interface trap density <5×10¹⁰ cm⁻²eV⁻¹ required for mobility preservation; post-deposition anneal (PDA) at 900-1000°C in N₂ for 5-30 seconds crystallizes HfO₂ and activates dopants
- Threshold Voltage Tuning: work function metal composition and thickness adjusted for multi-Vt libraries; NMOS Vt range 0.25-0.50V, PMOS -0.25 to -0.50V; channel doping minimized (<10¹⁷ cm⁻³) to preserve mobility; Vt primarily controlled by gate metal work function
Performance and Scaling:
- Drive Current Density: 3nm GAA achieves 1.8-2.2 mA/μm for NMOS, 1.4-1.7 mA/μm for PMOS at Vdd=0.75V, 100nA/μm off-current; 40-50% higher than FinFET at same footprint due to improved electrostatics and optimized nanosheet width
- Leakage Reduction: off-state leakage 2-3× lower than FinFET at equivalent performance; enables 0.65-0.70V operation for ultra-low-power applications; subthreshold slope 65-70 mV/decade maintained to 10nm gate length
- Variability Control: random dopant fluctuation (RDF) eliminated by undoped channels; line-edge roughness (LER) of nanosheet edges becomes dominant variability source; σVt <15mV achieved with <1nm LER control
- 2nm and Beyond: nanosheet thickness scales to 3-4nm; width reduces to 8-12nm; gate length approaches 10nm; stacked nanosheet count increases to 5-6 for drive current maintenance; complementary FET (CFET) with vertically stacked NMOS/PMOS under development for 1nm node
Gate-All-Around transistors represent the most significant transistor architecture transition since the introduction of FinFETs in 2011 — their superior electrostatic control and design flexibility enable continued Moore's Law scaling through the 3nm, 2nm, and 1nm nodes, maintaining the semiconductor industry's 50-year trajectory of exponential performance improvement.