High-k Metal Gate (HKMG) Integration at Advanced Nodes is the sophisticated process sequence that replaces traditional SiO₂/polysilicon gate stacks with hafnium-based high-k dielectrics and multi-layer metal electrodes, enabling continued equivalent oxide thickness (EOT) scaling below 0.7 nm while suppressing gate leakage and maintaining threshold voltage control at sub-5 nm technology nodes.
High-k Dielectric Stack Engineering:
- Interfacial Layer (IL): ultra-thin SiO₂ (0.3-0.5 nm) formed by chemical oxidation or ozone treatment at the Si/high-k interface to maintain carrier mobility—thinner IL reduces EOT but increases interface trap density (Dit)
- HfO₂ Deposition: 1.0-1.8 nm HfO₂ deposited by thermal ALD using TDMAH or HfCl₄ precursors at 250-300°C with H₂O co-reactant, achieving dielectric constant (k) of 20-25
- La₂O₃ Doping: 0.2-0.5 nm lanthanum oxide capping layer diffuses into HfO₂ during anneal, creating dipole that shifts NMOS Vt by 100-200 mV without additional doping
- Al₂O₃ Capping: aluminum oxide capping for PMOS work function adjustment, providing 200-300 mV Vt shift through interface dipole formation
- Post-Deposition Anneal: spike anneal at 850-950°C for 1-5 seconds crystallizes HfO₂ into higher-k tetragonal/cubic phases while minimizing IL regrowth
Replacement Metal Gate (RMG) Process Flow:
- Dummy Gate Formation: sacrificial polysilicon gate patterned with hardmask using EUV lithography at 28-48 nm gate pitch
- Source/Drain Processing: epitaxial S/D growth, ILD₀ deposition, and CMP planarization performed with dummy gate in place
- Dummy Gate Removal: selective wet/dry etch removes polysilicon stopping on thin SiO₂ etch stop—requires >1000:1 selectivity to surrounding SiN spacers
- Gate-First vs Gate-Last: gate-last RMG process avoids exposing high-k/metal gate to high-temperature S/D activation anneals (>1000°C)
Multi-Layer Work Function Metal Stack:
- NMOS Stack: TiN barrier (0.5-1.0 nm) / TiAl work function metal (2-4 nm) / TiN cap (1-2 nm)—effective work function (EWF) target 4.1-4.3 eV
- PMOS Stack: TiN (2-5 nm) / TaN (1-2 nm)—EWF target 4.8-5.0 eV, leveraging aluminum-free stack to maintain high work function
- Multi-Vt Integration: selective TiN thickness modulation through dipole engineering and metal layer variation provides 3-5 Vt options (uLVT, LVT, SVT, HVT) spanning 300 mV range
- Deposition Control: ALD metal films require thickness control within ±0.1 nm—single atomic layer variations cause 10-30 mV Vt shifts
Gate Fill and CMP Challenges:
- Tungsten Fill: CVD W using WF₆/SiH₄ chemistry fills remaining gate trench volume; nucleation layer thickness minimized to <2 nm to maximize fill volume
- Ruthenium Alternative: Ru gate fill offers lower resistivity (7.1 µΩ-cm vs 20+ µΩ-cm for thin W films) and void-free fill in ultra-narrow trenches below 10 nm width
- Gate CMP: multi-step CMP removes overburden metal with high selectivity to ILD—dishing and erosion must be <1 nm for multi-Vt uniformity
Advanced Node Scaling Challenges:
- EOT Floor: fundamental limit around 0.5-0.6 nm due to IL thickness requirements and high-k crystallization constraints
- Nanosheet Integration: HKMG must wrap around 3-4 stacked nanosheets with uniform thickness in 3-5 nm inter-sheet gaps—requires exceptional ALD conformality
- Ferroelectric HfO₂: doped HfO₂ (Si, Zr, La) exhibiting ferroelectric behavior enables negative capacitance FETs (NCFETs) for sub-60 mV/decade switching
High-k metal gate integration remains the most critical module in advanced CMOS processing, where angstrom-level control of dielectric and metal film thicknesses across complex 3D transistor geometries directly determines the threshold voltage, leakage current, and reliability characteristics that define each technology node's competitive position.