Gate Dielectric Scaling and EOT is the continual reduction of the effective electrical thickness of the gate insulator stack, measured as Equivalent Oxide Thickness (EOT), to maintain strong electrostatic control of the transistor channel as gate lengths shrink below 10nm — the central challenge of transistor scaling since the introduction of high-k dielectrics at 45nm. EOT reduction directly increases gate capacitance per unit area → stronger gate control → lower subthreshold slope → ability to scale VDD while maintaining drive current.

Equivalent Oxide Thickness (EOT)

• EOT = physical thickness × (k_SiO₂ / k_material) — normalizes any dielectric to its equivalent SiO₂ thickness.
• Lower EOT = thinner electrical insulator = stronger gate control.
• Formula: EOT_total = EOT_interfacial_oxide + EOT_high-k + EOT_metal_gate_penetration.
• Target progression: 45nm → 1.3 nm EOT; 28nm → 1.0 nm; 14nm → 0.7 nm; 5nm → 0.5 nm.

Gate Dielectric Stack Components

Metal Gate (TiN, TaN)
      ↓
High-k Dielectric (HfO₂, 1.5–2.5 nm physical, k=22)
      ↓
Interfacial Layer (SiO₂ or SiON, 0.5–1.0 nm physical, k=3.9)
      ↓
Si Channel

The Interfacial Layer (IL) — EOT Bottleneck

• A thin SiO₂ or SiON layer at Si/high-k interface is required for interface quality (low Dit).
• IL cannot be eliminated — removing it degrades interface trap density (Dit > 10¹¹ cm⁻² eV⁻¹) → degraded subthreshold slope, reliability.
• IL thickness limits EOT scaling: IL contributes most to EOT (k=3.9 → poor EOT efficiency).
• At 5nm node: IL thickness ~0.5 nm → contributes 0.5 nm EOT → dominant component.

High-k Materials for EOT Reduction

HfO₂ — The Industry Standard High-k

• Thermally stable on Si up to 900°C → compatible with CMOS anneals.
• Deposited by ALD for conformal, pinhole-free coverage.
• Monoclinic phase (low k ~18) vs. cubic/tetragonal phase (k ~22–28) — phase tuning by annealing and dopants.
• La-doped HfO₂: Stabilizes high-k phase → k increases → better EOT at same physical thickness.

EOT Scaling Strategies

• IL thinning: Careful pre-clean + controlled re-oxidation → 0.5 nm IL.
• High-k thickening: More HfO₂ physical thickness → better gate control per nm EOT.
• La doping of HfO₂: Increase k → same physical thickness → lower EOT.
• Metal gate penetration control: Some WF metals oxidize at IL interface → increase EOT → must minimize.
• Nitridation of IL: Convert SiO₂ IL to SiON (k ~5–6) → reduces IL EOT contribution by 20–30%.

Gate Leakage vs. EOT

• As EOT decreases → direct tunneling leakage increases exponentially.
• Pure SiO₂ at 0.5 nm EOT → gate leakage ~10 A/cm² → unacceptable.
• HfO₂ at 0.5 nm EOT (physical 2.5 nm) → gate leakage ~10⁻³ A/cm² → acceptable.
• High-k keeps physical thickness large → tunneling suppressed despite thin electrical EOT.

Ferroelectric HfO₂ — Future Direction

• Doped HfO₂ (Zr, Si, Y, La) can be made ferroelectric → used for FeFET memory.
• Also: Negative capacitance FETs — ferroelectric gate → sub-60 mV/decade subthreshold slope possible.

Gate dielectric scaling and EOT reduction is the electrostatic engineering discipline that keeps transistor performance improving despite physical thickness limits — by replacing SiO₂ with high-k materials that maintain a large physical distance between gate metal and channel while maintaining strong electrical control, EOT scaling has enabled gate lengths to shrink from 130nm to 8nm over two decades while maintaining the channel electrostatic integrity essential for functional, efficient transistors.