Gate oxide is the critical thin dielectric layer between the transistor channel and gate electrode that controls transistor switching and determines key electrical parameters. Thickness: Has scaled from ~100nm in early CMOS to <1nm equivalent oxide thickness (EOT) at advanced nodes. Quality requirements: Must be defect-free, uniform, and reliable. Single pinhole or weak spot can cause device failure. Thermal oxide: Historically grown by dry thermal oxidation. Highest quality Si/SiO2 interface with minimal defects (~10^10/cm² interface states). High-k dielectrics: Below ~1.5nm SiO2, tunneling leakage becomes unacceptable. HfO2-based high-k replaced SiO2 starting at 45nm node. Higher physical thickness for same EOT = lower leakage. Interface layer: Thin SiO2 or SiON interfacial layer (~0.3-0.5nm) between Si channel and high-k dielectric maintains interface quality. EOT: Equivalent Oxide Thickness - physical thickness of high-k film scaled by dielectric constant ratio. k(HfO2)~25 vs k(SiO2)~3.9. Reliability: Gate oxide must survive 10+ years of operation. TDDB (Time-Dependent Dielectric Breakdown) is key reliability test. Vt control: Gate oxide thickness directly affects threshold voltage. Thickness uniformity critical for Vt matching. Pre-gate clean: Wafer surface cleanliness before gate oxide growth/deposition is extremely critical. Any contamination degrades oxide quality. Scaling history: Gate oxide scaling has been a primary driver of MOSFET performance improvement across technology nodes.