Gate Patterning and Gate Etch is the lithography and plasma etch sequence that defines the gate electrode critical dimension (CD) — the most performance-critical dimension on the chip — where a ±1 nm change in gate length directly changes transistor threshold voltage by 10–30 mV and drive current by 5–10%, propagating directly into circuit timing and power. Gate patterning is the highest-stakes etch process in CMOS manufacturing, combining extreme CD control, profile uniformity, and etch selectivity in a single integrated sequence.

Gate Patterning in Poly Gate Era (Pre-HKMG)

1. Gate oxide growth (SiO₂ or oxynitride)
2. Polysilicon deposition (LPCVD, 100–150 nm)
3. Hard mask deposition (SiN or SiO₂, 20–40 nm)
4. Photoresist coat + EUV/ArFi lithography
5. Hard mask etch (anisotropic CHF₃/CF₄ plasma)
6. Resist strip
7. Poly etch (Cl₂/HBr plasma, high selectivity to gate oxide)
8. Breakthrough etch → stop on gate oxide
9. Gate oxide trim etch (dilute HF or dry)

Replacement Metal Gate (RMG / Gate-Last) Patterning

• At high-k/metal gate nodes (28nm and below), actual metal gate is formed AFTER S/D processing (gate-last).
• First, poly dummy gate is patterned → serves as placeholder.
• After S/D, ILD CMP, the dummy poly is removed → metal gate fills the resulting trench.
• This means gate CD is defined by the dummy poly pattern AND subsequent CMP planarization.

CD Control Requirements

Poly Gate Etch Chemistry

• Cl₂ + HBr plasma: HBr provides selectivity to gate oxide; Cl₂ promotes lateral Si etch for good CD.
• Sidewall passivation: SiBrₓ or SiOₓ formed on sidewalls during etch → controls profile angle (88–90°).
• Main etch: High selectivity to hard mask and gate oxide (poly:oxide selectivity >100:1).
• Over-etch: Lower power, Cl₂-rich → removes poly residues in field without attacking gate oxide.
• Endpoint: OES (optical emission spectroscopy) monitors Si etch signal → detects gate oxide breakthrough.

Gate Profile Metrics

Hard Mask Approach

• Thick photoresist alone cannot withstand the long gate etch → hard mask (SiN or TEOS) used.
• Hard mask provides better CD stability during poly etch → more precise gate bottom CD.
• Multi-layer hard mask (BARC + oxide + SiN) used at 10nm and below for extra etch budget.

Gate Etch in FinFET

• Gate wraps over fin → etch must clear gate material from fin sidewalls AND fin tops simultaneously.
• Higher aspect ratio than planar → stronger tendency for microloading and profile variation.
• Over-etch: Must clear fin sidewalls without over-etching fin foot into STI oxide → narrow process window.

Gate Etch in GAA Nanosheet

• Dummy poly gate patterned over nanosheet stack → same etch sequence as FinFET dummy gate.
• After gate-last flow: Metal gate trench is very narrow (8–12 nm wide, 50–100 nm deep) → metal fill by ALD.
• Gate CD in GAA set by dummy poly etch + dummy gate removal etch + metal ALD thickness.

Gate patterning and etch is the single most CD-critical manufacturing step in CMOS — where angstrom-level precision determines whether a transistor meets its performance target, and where the interplay between lithography, etch chemistry, sidewall passivation, and hard mask selection defines the fundamental frequency and power of every circuit from smartphone SoC to data center processor.