Global Routing and Detail Routing are the two-stage process that determines the physical paths of all metal wires connecting logic cells on a chip — where global routing plans coarse wire paths across the chip to manage congestion, and detail routing assigns exact metal tracks, vias, and spacing that satisfy all design rules in the final layout.

Two-Stage Routing

Global Routing

1. Chip divided into rectangular grid tiles (GCells — Global Cells). 2. Each tile has limited routing capacity (tracks per metal layer). 3. Global router assigns each net to a sequence of tiles — minimizing total wire length and congestion. 4. Congestion map: Shows which tiles are over-capacity — guides cell placement optimization. 5. Algorithms: Maze routing (Lee's algorithm), Steiner tree, A* search, negotiation-based (PathFinder).

Detail Routing

1. Within each tile, assign nets to specific metal tracks. 2. Insert vias for layer transitions. 3. Satisfy all DRC rules: spacing, width, enclosure, minimum area. 4. Handle obstacles: Blockages, pre-routed power rails, clock nets. 5. Optimize: Minimize via count (vias add resistance), reduce wirelength, fix DRC violations.

Routing Challenges at Advanced Nodes

• Routing resource scarcity: At 3nm, M1/M2 pitch ~22-28 nm → fewer tracks per cell height.
• Via resistance: Each via adds ~5-20 Ω — multiple vias in series degrade signal timing.
• Double/triple patterning constraints: Metal tracks must be assigned to specific mask colors — limits routing flexibility.
• Self-aligned vias: Vias must align to predefined grid positions — constrains layer-to-layer connectivity.

EDA Router Tools

• Innovus (Cadence): Industry-leading router with NanoRoute engine.
• IC Compiler II (Synopsys): Zroute engine for advanced node routing.
• Fusion Compiler (Synopsys): Unified synthesis + P&R with router-in-the-loop optimization.

Routing Metrics

• DRC violations: Target zero after detail routing.
• Overflow: Global routing cells exceeding capacity → indicates placement must improve.
• Via count: Lower is better for resistance and yield.
• Wirelength: Total routed wire → affects capacitance and power.

Global and detail routing are where the abstract logic design becomes physical metal on silicon — the router's ability to find valid paths for millions of nets while satisfying thousands of design rules determines whether a chip can be manufactured and whether it meets its performance targets.