GPU memory is the hierarchy that stores and moves instructions, model parameters, activations, caches, and intermediate tensors for graphics and accelerator execution. For modern AI, capacity and delivered bandwidth are often more limiting than nominal arithmetic throughput. A discrete GPU may combine per-thread registers, per-block or per-SM shared memory, L1 and texture caches, a shared L2, and external HBM or GDDR; host DRAM and storage sit beyond device links. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. HBM3E-class products use several stacked memories and wide package interfaces, with product configurations spanning tens to well over one hundred gigabytes and aggregate bandwidth from roughly two to several terabytes per second. Exact stack count, capacity, and rate are device-specific.

Architecture, quantitative model, and operating behavior. Registers offer the lowest latency and highest locality but are private and scarce. Programmer-managed shared memory enables tile reuse. L1/L2 caches capture temporal and spatial locality. HBM supplies capacity and bandwidth, while host DRAM extends capacity at much lower effective device access rate. Loads are issued by warps or wavefronts, coalesced into transactions, served from caches or external memory, and hidden through concurrency. Allocators reserve virtual ranges and physical pages; CUDA unified virtual memory and related systems share a virtual address space and migrate or map pages between CPU and GPU. HBM favors wide interfaces and bandwidth near the package; GDDR favors simpler board attachment; integrated GPUs may share system DRAM; coherent accelerator memory can participate in a larger address space. ECC, compression, partitioning, and confidential-memory features change usable capacity and cost. Useful analysis separates arithmetic, memory hierarchy, interconnect, storage, control, and queuing. It counts operations and bytes at each boundary, identifies dependencies and reuse, estimates ideal ceilings, and then uses counters and traces to explain the gap between the model and measurement. Ratios without a clearly named numerator and denominator invite invalid comparisons. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints.

Implementation, hardware mapping, and bottlenecks. Optimize layouts, aligned coalesced accesses, tile reuse, fusion, prefetch, async copies, lifetime planning, pooling allocators, checkpointing, and cache-aware attention. Separate reserved from allocated memory and account for fragmentation, workspace, graph capture, KV cache, and communication buffers. Register pressure reduces occupancy, bank conflicts serialize shared memory, cache thrashing raises HBM traffic, TLB misses and page faults stall migration, and PCIe oversubscription makes oversubscribed memory unpredictable. Out-of-memory can arise from peaks or fragmentation rather than model size; unified-memory oversubscription can thrash; an HBM headline ignores cache and access efficiency; host-device copies can dominate a kernel speedup. Begin with a correct reference and representative shapes. Profile end to end, classify the dominant resource, inspect kernel and system timelines, change one bottleneck at a time, and remeasure because optimization moves pressure elsewhere. Tiling, fusion, batching, vectorization, layout, precision, compression, overlap, prefetch, sharding, and algorithm choice are useful only when they reduce the limiting resource. The execution path spans registers, local SRAM and caches, HBM or GDDR, host DRAM, PCIe or coherent links, scale-up fabric, network, and storage. Compute units consume tensors only when compilers and kernels issue enough independent work and the hierarchy supplies operands. Package wiring, memory stacks, clocks, voltage, thermal headroom, and power delivery determine sustained limits. Frequent mistakes include quoting peak instead of achieved rates, omitting data conversion and transfer, measuring a cached toy input, timing asynchronous work without synchronization, mixing decimal and binary units, ignoring warmup or throttling, changing precision or quality, averaging away tails, and optimizing a component that is not on the critical path.

Measurement, validation, and engineering controls. Measure capacity high-water marks, bandwidth by level, cache and TLB behavior, transactions per request, page migrations, allocator fragmentation, stalls, and kernel time across representative sequences and batches. Bytes per parameter/token, KV-cache growth, achieved versus peak bandwidth, latency, hit rate, occupancy, page-fault cost, allocation time, and energy per transferred byte matter. Allocation snapshots, memory timelines, leak tests, page-fault traces, and controlled stride/reuse microbenchmarks distinguish capacity, locality, and bandwidth problems. Verification combines analytical bounds, microbenchmarks, hardware counters, kernel timelines, end-to-end traces, scaling sweeps, sensitivity to batch and shape, cold and warm runs, long-duration thermal tests, correctness comparisons, fault and congestion tests, and independent reproduction. Roofline and queueing models guide diagnosis but must be calibrated against the deployed machine. Benchmark code, datasets, model and compiler artifacts, drivers, firmware, topology, clock and power settings, environment, commands, raw samples, counter traces, and analysis notebooks remain versioned. Continuous tests detect regressions in quality, latency, throughput, bandwidth, memory, power, and cost, with thresholds chosen from variance rather than a single run. Published comparisons disclose configuration, exclusions, tuning effort, measurement boundary, quality criteria, and uncertainty. Energy and carbon claims distinguish chip, IT, and facility boundaries and avoid extrapolating one benchmark to all workloads. Owners review regressions and retain evidence sufficient to reproduce decisions.

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Selection and system-level application. Choose HBM for bandwidth-intensive accelerators, GDDR where board economics dominate, shared system memory for integrated designs, and managed memory for productivity only after migration behavior is bounded. LLM training and decode, recommendation embeddings, vision, simulation, rendering, graph analytics, and scientific computing depend on GPU memory behavior. Model architecture, precision, batching, parallelism, compiler fusion, allocator, memory topology, package, cooling, and interconnect determine the usable hierarchy. Optimization is a system exercise across algorithms, precision, kernels, compiler, runtime, accelerator, memory, interconnect, scheduler, serving policy, cooling, and facility limits. Removing one ceiling often exposes another, so architecture decisions should optimize time and energy to a useful result rather than an isolated metric. A professional performance claim defines workload, useful work, input and output shapes, numerical format, batch and concurrency, warmup and measurement interval, hardware and software versions, power state, correctness tolerance, and aggregation method. Peak specifications are ceilings under particular conditions; delivered behavior includes utilization, data movement, synchronization, control overhead, and tail effects. Report useful throughput together with latency distribution, utilization, arithmetic intensity, achieved bandwidth, cache hit rate, occupancy, communication time, memory capacity, power, energy per result, quality, and cost. Include median and tail behavior, sustained rather than burst operation, repeated trials, and uncertainty. A faster approximation is not equivalent unless it meets the same accuracy and service constraints. CFS connects this topic to semiconductor architecture, implementation, verification, manufacturing, packaging, test, and deployed AI-system tradeoffs across the platform.