The H-gate is a transistor layout geometry for partially-depleted silicon-on-insulator (PD-SOI) devices where the gate electrode is shaped like the letter H, with the horizontal crossbar forming the active gate over the channel and the two vertical legs extending to make direct contact with the body, integrating body potential control directly into the gate footprint. In PD-SOI, the thin buried oxide electrically isolates the transistor body from the substrate beneath, which improves performance by reducing junction capacitance and eliminating latchup, but creates a new problem: if the body is left electrically floating, it accumulates charge during operation — impact-ionization holes in NMOS, for example — and its potential drifts unpredictably, shifting threshold voltage, degrading output resistance, and introducing kink effects in the I-V curve. The H-gate solves this by turning the gate itself into a dual-purpose structure that both controls the channel and ties the body to a fixed potential, eliminating floating-body effects without the area overhead of separate body-contact regions placed away from the gate.

Layout mechanics. The gate polysilicon is drawn in an H shape in plan view: the horizontal bar runs perpendicular to source and drain and forms the active transistor gate in the usual way, while the two vertical legs of the H extend beyond the active channel region to land on diffusion regions tied to the body. Because SOI transistors sit on a thin silicon film isolated from the substrate, the body is accessible as a separate terminal at the same silicon level as source and drain, so the vertical legs of the H can make ohmic contact to it using the same diffusion and silicide processes used for source and drain contacts — no special contact scheme is required, just a deliberate extension of the gate shape to reach the body tie regions.

Floating-body suppression. By tying the body directly to a known potential — typically source potential in digital logic, or an independent bias in analog designs — the H-gate prevents the parasitic bipolar effects that floating bodies enable: in a floating-body NMOS, holes generated by impact ionization accumulate in the body, forward-bias the body-source junction, inject minority carriers, and create a parasitic NPN current path that produces the characteristic kink in the drain current curve and a history-dependent threshold voltage. With the body hard-tied via the H-gate legs, excess charge is immediately sunk to the body contact rather than accumulating, so $V_T$ stays constant and the kink disappears.

Analog circuit motivation. While digital circuits can sometimes tolerate floating-body effects or use other mitigation techniques (body-tied source in pass gates, periodic refresh in DRAM-style retention), analog circuits — particularly those relying on high output resistance for gain, precise matching for differential pairs, or stable bias points for current mirrors — cannot afford the threshold-voltage drift and transconductance variation that a floating body introduces. The H-gate was a standard layout practice in the PD-SOI analog design kits from IBM, AMD, and others in the early 2000s, when PD-SOI was positioned as a performance and low-power alternative to bulk CMOS for mixed-signal SoCs, before the industry pivot to FD-SOI (which intrinsically suppresses floating-body effects through full depletion, making the H-gate unnecessary) and FinFETs (which are effectively self-body-tied in a different way).

Area efficiency. The H-gate's key advantage over alternative body-contact schemes — such as T-contacts (separate diffusion stripes placed perpendicular to the gate) or dedicated body-tie transistors scattered across the layout — is that it integrates the body contact into the gate footprint itself, so the contact consumes no additional layout pitch and the transistor can be packed into a compact, regular array. The tradeoff is gate resistance: the vertical legs of the H add extra polysilicon length in the gate path, increasing gate resistance slightly, which matters for RF and very high-speed digital circuits where gate RC delay is significant, but is negligible for the moderate-frequency analog blocks that were the H-gate's primary target.

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Current relevance. H-gate layouts are now largely historical, tied to the PD-SOI era. FD-SOI and FinFET technologies resolve floating-body issues through their intrinsic device physics rather than layout geometry, so the H-gate trick is no longer needed — but it remains a clean example of how layout geometry can directly solve a device-physics problem when the process technology leaves a degree of freedom (body contact placement) under designer control.