Half-pitch is half of the center-to-center distance between repeating equal lines and spaces in a dense grating on a semiconductor wafer, serving as the historical gold-standard metric for defining optical lithography resolution, Rayleigh diffraction limits, and international semiconductor technology roadmap milestones. For an equal line-and-space pattern where the critical dimension (CD) of the printed line equals the adjacent space width ($w_{\text{line}} = w_{\text{space}}$), half-pitch is mathematically identical to the line width itself ($HP = P/2 = CD$). Historically, each technology node generation was named after its printed half-pitch—from the $10\ \mu\text{m}$ nodes of the 1970s down to the $22\text{ nm}$ immersion node—before 3D device architectures, multi-patterning, and standard-cell height reduction decoupled marketing node names from physical 1D half-pitch dimensions.

The Rayleigh criterion defines minimum printable half-pitch as a function of wavelength, numerical aperture, and illumination coherence. In optical lithography, the fundamental limit for resolving a dense periodic grating is governed by the classical Abbe-Rayleigh relationship:

where $\lambda$ is the exposure light wavelength ($193\text{ nm}$ for ArF excimer lasers, $13.5\text{ nm}$ for extreme ultraviolet sources), $\text{NA} = n\sin\theta$ is the numerical aperture of the projection optics, and $k_1$ is the dimensionless process difficulty factor. Under symmetrical on-axis illumination, collecting the zero and $\pm 1$ diffraction orders requires $k_1 \ge 0.50$. By adopting extreme off-axis illumination (OAI) such as dipole or quadrupole sources, the zeroth and one first-order diffraction beam pass through opposite edges of the pupil lens, reducing the theoretical single-exposure physical lower bound to $k_1 = 0.25$.

Equal line-and-space gratings represent the most demanding optical challenge for scanner image contrast. For isolated lines or contact holes, optical proximity correction (OPC) can use sub-resolution assist features (SRAF) to tailor the wavefront. In dense gratings where the half-pitch approaches the Rayleigh limit, higher spatial harmonic frequencies are completely lost outside the lens pupil aperture, transforming the square-wave mask transmission into a pure sinusoidal aerial image intensity:

where $m$ is the image modulation contrast ($m = (I_{\text{max}} - I_{\text{min}}) / (I_{\text{max}} + I_{\text{min}})$). As half-pitch shrinks toward the diffraction boundary, contrast $m$ degrades, narrowing the exposure latitude and increasing vulnerability to photoresist blur, line edge roughness (LER), and stochastic nano-bridging.

Pitch splitting and self-aligned spacer deposition scale physical half-pitch beyond optical diffraction floors. When single exposure reached the $k_1 \approx 0.28$ limit in 193 nm immersion lithography ($\text{HP} \approx 38\text{ nm}$), foundries implemented Self-Aligned Double Patterning (SADP). By defining initial mandrels at pitch $P_0$, depositing conformal oxide spacers of thickness $W_{\text{spacer}} = \text{HP}_{\text{target}}$, and selectively etching the core, the effective half-pitch was halved without changing optical wavelength:

Through SAQP, immersion DUV scanners achieved $10\text{--}14\text{ nm}$ half-pitches in production, though at the expense of quadrupled mask counts, severe overlay sensitivity, and complex block-mask integration.

The commercial technology node naming convention decoupled from physical half-pitch at the 22nm generation. Prior to the 2010s, the International Technology Roadmap for Semiconductors (ITRS) classified technology nodes by their dense metal or DRAM half-pitch ($180\text{ nm}, 130\text{ nm}, 90\text{ nm}, 65\text{ nm}, 45\text{ nm}, 32\text{ nm}, 22\text{ nm}$). As planar MOSFETs reached physical electrostatics limits, foundries introduced 3D FinFETs, gate-all-around (GAA) nanosheets, and standard-cell track reductions ($6\text{T}$ to $5\text{T}$ cells). Consequently, modern commercial node designations ("3nm", "2nm", "A14") reflect equivalent logic density scaling rather than physical gate or interconnect half-pitch: a leading-edge "3nm" node operates with a minimum metal half-pitch of $12\text{--}14\text{ nm}$ ($24\text{--}28\text{ nm}$ pitch) and a contacted poly half-pitch of $24\text{ nm}$ ($48\text{ nm}$ CPP).

High-NA EUV lithography reduces half-pitch below 10 nanometers using anamorphic magnification optics. To overcome the resolution limit of conventional $0.33\ \text{NA}$ EUV scanners ($\text{HP} \approx 13\text{ nm}$), $0.55\ \text{NA}$ High-NA EUV systems incorporate anamorphic reflection mirrors ($4\times$ magnification in the scanning direction, $8\times$ in the cross-scan direction). This optical design prevents light from striking the EUV photomask at high angles that would exceed multilayer Bragg reflection limits, enabling single-exposure half-pitches down to $\text{HP} \approx 8\text{ nm}$ ($16\text{ nm}$ full pitch) while eliminating multiple-exposure stochastic overlay error.

st=>start: Define target circuit density and standard cell architecture
calc=>operation: Compute required minimum metal half-pitch HP = P_min / 2
check=>condition: HP ≥ 13nm (Achievable with 0.33 NA EUV single exposure)?
single=>operation: Deploy 0.33 NA EUV with optimized resist and pupil illumination
highna=>condition: HP ≥ 8nm (Achievable with 0.55 High-NA EUV single exposure)?
anamorph=>operation: Deploy 0.55 High-NA anamorphic EUV with stitched half-fields
multi=>operation: Implement EUV pitch splitting (EUV SADP) or 3D CFET vertical integration
qual=>end: Qualified dense half-pitch patterning baseline for manufacturing
st->calc->check
check(yes)->single->qual
check(no)->highna
highna(yes)->anamorph->qual
highna(no)->multi->qual

Mastering modern device scaling requires treating half-pitch as a fundamental-diffraction-limit-and-dense-grating-resolution lens. Whether evaluated in memory bitlines, dense logic routing, or transistor fin arrays, half-pitch represents the exact boundary where photon wavelengths, photoacid diffusion kinetics, and mechanical scanner tolerances govern yield. Precision engineering bridges this boundary through rigorous optical proximity corrections, stochastic defect mitigation, and co-optimization with advanced materials and 3D device architectures.