Hardmask Patterning in Semiconductor Etch

Keywords: hardmask etch,silicon nitride hardmask,carbon hardmask,ashable hardmask,patterning hardmask,hard mask stack

Hardmask Patterning in Semiconductor Etch is the use of inorganic or dense carbon films as etch-resistant intermediate layers between the photoresist and the target film β€” since photoresist alone lacks the etch resistance to withstand deep or long silicon, oxide, or metal etches, hardmasks allow the lithographic image to be transferred first into a durable material that can then faithfully transfer the pattern into the underlying target layer with the required etch depth and profile precision.

Why Hardmasks Are Needed

- Photoresist selectivity to Si, SiOβ‚‚: Poor (1:1 to 5:1) β†’ resist consumed before etch complete.
- Deep etch (HARC, STI): Aspect ratio > 5:1 β†’ resist would be fully consumed before etch stops.
- Thin resist (immersion, EUV): Thinner resist for resolution β†’ even less etch budget β†’ hardmask essential.
- Solution: Transfer pattern into hardmask first (fast, easy etch), then etch target with hardmask.

Common Hardmask Materials

| Material | Deposition | Selectivity to Si | Selectivity to SiOβ‚‚ | Uses |
|----------|----------|------------------|--------------------|------|
| SiOβ‚‚ | TEOS PECVD | 50:1 | β€” | Gate poly etch |
| SiN (Si₃Nβ‚„) | PECVD/LPCVD | 20:1 | 5:1 | STI etch cap |
| TiN | PVD/ALD | High | High | Via/contact etch |
| APF (amorphous C) | CVD | 100:1 | 50:1 | Deep silicon/HARC |
| Spin-on C (SOC) | Spin | 50:1 | 30:1 | Patterning stacks |

Advanced Patterning Hard Mask Stack

- Modern multi-patterning: Complex hardmask stacks with 3–5 layers.
- Typical EUV/193i patterning stack (top to bottom):
- Thin resist (30–50 nm)
- SiARC (Silicon Anti-Reflective Coating) β€” thin SiOβ‚‚-like, 10–20 nm
- Spin-on carbon (SOC) β€” thick organic, 100–200 nm β†’ high etch resistance
- SiN or TiN hardmask β€” inorganic, 20–30 nm β†’ etch selectivity to target
- Target film (SiOβ‚‚, poly, metal, etc.)

Amorphous Carbon (APF) Hardmask

- Applied Materials APF (Advanced Patterning Film): CVD carbon at 400Β°C β†’ very dense carbon film.
- Composition: > 95% carbon, sp3 hybridized β†’ diamond-like hardness β†’ excellent etch resistance.
- Thickness: 100–500 nm β†’ sufficient for HARC etch (> 50:1 AR).
- Ashable: Oβ‚‚ plasma β†’ burns off carbon β†’ no residue, no CMP needed.
- Selectivity: SiOβ‚‚:APF in fluorocarbon etch β‰ˆ 50:1 β†’ APF survives while oxide etches through.

Titanium Nitride (TiN) Hardmask

- Excellent etch resistance to fluorine and chlorine plasmas.
- Used for: Via etch (must survive long oxide etch), gate replacement (RMG via etch stop).
- Deposition: ALD TiN (TiClβ‚„ + NH₃) β†’ conformal even at high AR.
- Removal: Wet (HF/Hβ‚‚Oβ‚‚) or dry (Clβ‚‚ plasma).

Pattern Transfer Flow

1. Coat hardmask stack on target film.
2. Expose photoresist β†’ develop β†’ resist pattern formed.
3. SiARC etch (dry) β†’ transfers resist pattern into SiARC.
4. SOC etch (Oβ‚‚/Nβ‚‚) β†’ transfers into thick carbon layer.
5. SiN hardmask etch (CFβ‚„) β†’ transfers into inorganic hardmask.
6. Resist + SOC removed (Oβ‚‚ strip β†’ ash).
7. Target film etch using SiN hardmask β†’ long, high-AR etch β†’ hardmask survives.
8. SiN hardmask removal (selective wet or dry) β†’ target pattern complete.

CD Budget in Hardmask Transfer

- Each etch transfer step may shift CD β†’ CD bias must be modeled and compensated.
- Isotropic undercut: If hardmask etch has lateral component β†’ trimming of CD.
- Directional bias: Etch loading, plasma non-uniformity β†’ different CD at dense vs isolated.
- OPC accounts for hardmask CD bias: Design layout biased so final pattern in target film = design intent.

Hardmask patterning is the mechanical engineering beneath the optical engineering of photolithography β€” by providing an etch-resistant intermediate layer that can be faithfully patterned by photoresist and then used to etch far deeper and more precisely than photoresist alone could survive, hardmasks extend the pattern transfer fidelity from the 50nm resist image all the way through 500nm of target material, enabling the deep contact holes, high-aspect-ratio vias, and precisely vertical gate stacks that define modern semiconductor device geometry and without which the combination of thin EUV resist and aggressive etch targets at leading nodes would be simply impossible to execute reliably.

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